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nuc121 /125 feb . 23 , 201 7 page 1 of 150 rev 1 .0 0 nuc121 /125 series datasheet arm cortex ? - m 0 32 - bit microcontroller numicro ? family nuc121 /125 series datasheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omi ssions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvoton.com
nuc121 /125 feb . 23 , 201 7 page 2 of 150 rev 1 .0 0 nuc121 /125 series datasheet table of contents 1 general description ................................ ................................ ...... 9 key features support table ................................ ................................ ......... 9 1.1 2 features ................................ ................................ ....................... 10 numicro ? nuc121/125 features ................................ ................................ ... 10 2.1 3 abbreviations ................................ ................................ .................... 16 abbreviations ................................ ................................ .......................... 16 3.1 4 parts information list and pin configuration ............................. 18 numicro ? nuc121/125 selection guide ................................ .......................... 18 4.1 4.1.1 numicro ? nuc121/125 naming rule ................................ ................................ ..... 18 4.1.2 numicro ? nuc121 usb series selection guide ................................ ........................ 19 4.1.3 numicro ? nuc125 usb series selection guide ................................ ........................ 19 pin configuration ................................ ................................ ...................... 20 4.2 4.2.1 numicro ? nuc121 qfn 33 - pin diagram ................................ ................................ . 20 4.2.2 numicro ? nuc121 qfn 33 - pin function diagram ................................ ...................... 21 4.2.3 numicro ? nuc121 lqfp 48 - pin diagram ................................ ................................ 22 4.2.4 numicro ? nuc121 lqfp 48 - pin function diagram ................................ .................... 23 4.2.5 numicro ? nuc121 lqfp 64 - pin diagram ................................ ................................ 24 4.2.6 numicro ? nuc121 lqfp 64 - pin function diagram ................................ .................... 25 4.2.7 numicro ? nuc125 qfn 33 - pin diagram ................................ ................................ . 26 4.2.8 numicro ? nuc125 qfn 33 - pin function diagram ................................ ...................... 27 4.2.9 numicro ? nuc125 lqfp 48 - pin diagram ................................ ................................ 28 4.2.10 numicro ? nuc125 lqfp 48 - pin function diagram ................................ .................... 29 4.2.11 numicro ? nuc125 lqfp 64 - pin diagram ................................ ................................ 30 4.2.12 numicro ? nuc125 lqfp 64 - pin function diagram ................................ .................... 31 pin description ................................ ................................ ........................ 32 4.3 4.3.1 nuc121 usb series qfn33 pin description ................................ ............................ 32 4.3.2 nuc121 usb series lqfp48 pin description ................................ .......................... 37 4.3.3 nuc121 usb series lqfp64 pin description ................................ .......................... 44 4.3.4 nuc125 usb series qfn33 pin description ................................ ............................ 52 4.3.5 nuc125 usb series lqfp48 pin description ................................ .......................... 57 4.3.6 nuc125 usb series lqfp64 pin description ................................ .......................... 64 4.3.7 gpio multi - function pin summary ................................ ................................ ......... 72 5 block diagram ................................ ................................ .............. 78
nuc121 /125 feb . 23 , 201 7 page 3 of 150 rev 1 .0 0 nuc121 /125 series datasheet numicro ? nuc121/125 block diagram ................................ ............................ 78 5.1 6 functional description ................................ ................................ 79 arm ? cortex ? - m0 core ................................ ................................ .............. 79 6.1 system manager ................................ ................................ ...................... 81 6.2 6.2.1 overview ................................ ................................ ................................ ....... 81 6.2.2 system reset ................................ ................................ ................................ .. 81 6.2.3 powe r modes and wake - up sources ................................ ................................ ...... 88 6.2.4 system power distribution ................................ ................................ .................. 90 clock controller ................................ ................................ ....................... 92 6.3 6.3.1 overview ................................ ................................ ................................ ....... 92 6.3.2 clock generator ................................ ................................ ............................... 94 6.3.3 system clock and systick clock ................................ ................................ .......... 96 6.3.4 peripherals clock ................................ ................................ ............................. 98 6.3.5 power - down mode clock ................................ ................................ .................... 98 6.3.6 clock output ................................ ................................ ................................ ... 98 flash memory controller (fmc) ................................ ................................ .. 100 6.4 6.4.1 overview ................................ ................................ ................................ ..... 100 6.4.2 features ................................ ................................ ................................ ...... 100 general purpose i/o (gpio) ................................ ................................ ...... 101 6.5 6.5.1 overview ................................ ................................ ................................ ..... 101 6.5.2 features ................................ ................................ ................................ ...... 101 pdma controller (pdma) ................................ ................................ ......... 102 6.6 6.6.1 overview ................................ ................................ ................................ ..... 102 6.6.2 features ................................ ................................ ................................ ...... 102 timer co ntroller (tmr) ................................ ................................ ............ 103 6.7 6.7.1 overview ................................ ................................ ................................ ..... 103 6.7.2 featur es ................................ ................................ ................................ ...... 103 basic pwm generator and capture timer (bpwm) ................................ .......... 104 6.8 6.8.1 overview ................................ ................................ ................................ ..... 104 6.8.2 features ................................ ................................ ................................ ...... 104 pwm generator and capture timer (pwm) ................................ ................... 105 6.9 6.9.1 overview ................................ ................................ ................................ ..... 105 6.9.2 featur es ................................ ................................ ................................ ...... 105 watchdog timer (wdt) ................................ ................................ ............ 107 6.10
nuc121 /125 feb . 23 , 201 7 page 4 of 150 rev 1 .0 0 nuc121 /125 series datasheet 6.10.1 overview ................................ ................................ ................................ ..... 107 6.10.2 features ................................ ................................ ................................ ...... 107 window watchdog timer (wwdt) ................................ .............................. 108 6.11 6.11.1 overview ................................ ................................ ................................ ..... 108 6.11.2 features ................................ ................................ ................................ ...... 108 usci - universal serial control interface controller ................................ .......... 109 6.12 6.12.1 overview ................................ ................................ ................................ ..... 109 6.12.2 featu res ................................ ................................ ................................ ...... 109 usci - uart mode ................................ ................................ ................ 110 6.13 6.13.1 overview ................................ ................................ ................................ ..... 110 6.13.2 features ................................ ................................ ................................ ...... 110 usci - spi mode ................................ ................................ .................... 111 6.14 6.14.1 overview ................................ ................................ ................................ ..... 111 6.14.2 featu res ................................ ................................ ................................ ...... 111 usci - i 2 c mode ................................ ................................ .................... 113 6.15 6.15.1 overview ................................ ................................ ................................ ..... 113 6.15.2 features ................................ ................................ ................................ ...... 113 uart interface controller (uart) ................................ ............................... 114 6.16 6.16.1 overview ................................ ................................ ................................ ..... 114 6.16.2 features ................................ ................................ ................................ ...... 114 i 2 c serial interface controller (i 2 c) ................................ .............................. 116 6.17 6.17.1 overview ................................ ................................ ................................ ..... 116 6.17.2 features ................................ ................................ ................................ ...... 116 serial peripheral interface (spi) ................................ ................................ .. 117 6.18 6.18.1 overview ................................ ................................ ................................ ..... 117 6.18.2 features ................................ ................................ ................................ ...... 117 usb device controller (usbd) ................................ ................................ ... 118 6.19 6.19.1 overview ................................ ................................ ................................ ..... 118 6.19.2 features ................................ ................................ ................................ ...... 118 analog - to - digital converter (adc) ................................ ............................... 119 6.20 6.20.1 overview ................................ ................................ ................................ ..... 119 6.20.2 features ................................ ................................ ................................ ...... 119 7 application circuit ................................ ................................ ..... 120 8 electrical characteristics ................................ ....................... 122
nuc121 /125 feb . 23 , 201 7 page 5 of 150 rev 1 .0 0 nuc121 /125 series datasheet absolute maximum ratings ................................ ................................ ....... 122 8.1 dc electrical characteristics ................................ ................................ ...... 123 8.2 ac electrical characteristics ................................ ................................ ...... 131 8.3 8.3.1 external 4~24 mhz high speed crystal (hxt) input clock ................................ .......... 131 8.3.2 external 4~24 mhz high speed crystal (hxt) oscillator ................................ ............ 131 8.3.3 external 32.768 khz low speed crystal (lxt) input clock ................................ ......... 132 8.3.4 external 32.768 khz low speed crystal (lxt) oscillator ................................ ............ 132 analog characteristics ................................ ................................ ............. 135 8.4 8.4.1 12 - bit adc ................................ ................................ ................................ ... 135 8.4.2 ldo ................................ ................................ ................................ ........... 137 8.4.3 low - voltage reset ................................ ................................ ......................... 137 8.4.4 brown - out detector ................................ ................................ ......................... 137 8.4.5 power - on reset ................................ ................................ ............................. 138 8.4.6 temperature sensor ................................ ................................ ....................... 139 8. 4.7 usb phy ................................ ................................ ................................ ..... 140 flash dc electrical characteris ................................ ................................ .. 141 8.5 i 2 c dynamic characteristics ................................ ................................ ...... 142 8.6 spi dynamic characteristics ................................ ................................ ...... 143 8.7 8.7.1 dynamic characteristics of data input and output pin ................................ ............... 143 9 package dimensions ................................ ................................ .... 145 lqfp 64s (7x7x1.4 mm) ................................ ................................ .......... 145 9.1 lqfp 48l (7x7x1.4 mm) ................................ ................................ .......... 146 9.2 qfn 33z (5x5x0.8 mm) ................................ ................................ ............ 147 9.3 10 revision history ................................ ................................ .......... 149
nuc121 /125 feb . 23 , 201 7 page 6 of 150 rev 1 .0 0 nuc121 /125 series datasheet list of figures figure 4.1 - 1 numicro ? nuc121/125 selection code ................................ ................................ .... 18 figure 4.2 - 1 numicro ? nuc121 qfn 33 - pin diagram ................................ ................................ .. 20 figure 4.2 - 2 numicro ? nuc121 qfn 33 - pin function diagram ................................ ................... 21 figure 4.2 - 3 numicro ? nuc121 lqfp 48 - pin diagram ................................ ................................ 22 figure 4.2 - 4 numicro ? nuc121 lqfp 48 - pin function diagram ................................ ................. 23 figure 4.2 - 5 numicro ? nuc121 lqfp 64 - pin diagram ................................ ................................ 24 figure 4.2 - 6 numicro ? nuc121 lqfp 64 - pin function diagram ................................ ................. 25 figure 4.2 - 7 numicro ? nuc125 qfn 33 - pin diagram ................................ ................................ .. 26 figure 4.2 - 8 numicro ? nuc125 qfn 33 - pin function diagram ................................ ................... 27 figure 4.2 - 9 numicro ? nuc125 lqfp 48 - pin diagram ................................ ................................ 28 figure 4.2 - 10 numicro ? nuc125 lqfp 48 - pin function diagram ................................ ............... 29 figure 4.2 - 11 numicro ? nuc125 lqfp 64 - pin diagra m ................................ .............................. 3 0 figure 4.2 - 12 numicro ? nuc125 lqfp 64 - pin function diagram ................................ ............... 31 figure 5.1 - 1 numicro ? nuc121/125 block diagram ................................ ................................ ..... 78 figure 6.1 - 1 cortex ? - m0 block diagram ................................ ................................ ........................ 79 figure 6.2 - 1 system reset sources ................................ ................................ .............................. 82 figure 6.2 - 2 nreset reset waveform ................................ ................................ ......................... 85 figure 6.2 - 3 power - on reset (por) waveform ................................ ................................ ............ 85 figure 6.2 - 4 low voltage reset (lvr) waveform ................................ ................................ ......... 86 figure 6.2 - 5 brown - out detector (bod) waveform ................................ ................................ ....... 87 figure 6.2 - 6 power mode state machine ................................ ................................ ...................... 88 figure 6.2 - 7 numicro ? nuc121/125 power distribution diagra m ................................ ................. 91 figure 6.3 - 1 clock generator global view diagram ................................ ................................ ...... 93 figure 6.3 - 2 clock generator block diagram ................................ ................................ ................ 95 figure 6.3 - 3 system clock block diagram ................................ ................................ .................... 96 figure 6.3 - 4 hxt stop protect procedure ................................ ................................ ..................... 97 figure 6.3 - 5 systick clock control block diagram ................................ ................................ ....... 98 figure 6.3 - 6 clock source of clock output ................................ ................................ ................... 99 figure 6.3 - 7 clock output block diagram ................................ ................................ ..................... 99 figure 6.14 - 1 spi master mode application block diagram ................................ ........................ 111 figure 6.14 - 2 spi slave mode application block diagram ................................ .......................... 111 figure 6.15 - 1 i 2 c bus timing ................................ ................................ ................................ ....... 113 figure 8.3 - 1 typical crystal application circuit ................................ ................................ ........... 132 figure 8.3 - 2 typical crystal application circuit ................................ ................................ ........... 133 figure 8.4 - 1 power - up ramp condition ................................ ................................ ...................... 138
nuc121 /125 feb . 23 , 201 7 page 7 of 150 rev 1 .0 0 nuc121 /125 series datasheet figure 8.6 - 1 i 2 c timing diagram ................................ ................................ ................................ . 142 figure 8.7 - 1 spi master mode timing diagram ................................ ................................ .......... 143 figure 8.7 - 2 spi slave mode timing diagram ................................ ................................ ............ 144
nuc121 /125 feb . 23 , 201 7 page 8 of 150 rev 1 .0 0 nuc121 /125 series datasheet list of tables table 1.1 - 1 key features support table ................................ ................................ ......................... 9 table 3.1 - 1 list of abbreviations ................................ ................................ ................................ .... 17 table 4.1 - 1 numicro ? nuc121 usb series selection guide ................................ ........................ 19 table 4.1 - 2 numicro ? nuc125 usb series selection guide ................................ ........................ 19 table 4.3 - 1 nuc121 usb series qfn33 pin descri ption ................................ ............................ 36 table 4.3 - 2 nuc121 usb series lqfp48 pin description ................................ ........................... 43 table 4.3 - 3 nuc121 usb series lqfp64 pin description ................................ ........................... 51 table 4.3 - 4 nuc125 usb series qfn33 pin description ................................ ............................ 56 table 4.3 - 5 nuc125 usb series lqfp48 pin descripti on ................................ ........................... 63 table 4.3 - 6 nuc125 usb series lqfp64 pin description ................................ ........................... 71 table 4.3 - 7 nuc121/125 gpio multi - function table ................................ ................................ ..... 77 table 6.2 - 1 reset value of registers ................................ ................................ ............................ 84 table 6.2 - 2 power mode difference table ................................ ................................ .................... 88 table 6.2 - 3 clocks in power modes ................................ ................................ .............................. 89 table 6.2 - 4 condition of entering power - down mode again ................................ ......................... 90 table 6.3 - 1 clock stable count value table ................................ ................................ ................. 94
nuc121 /125 feb . 23 , 201 7 page 9 of 150 rev 1 .0 0 nuc121 /125 series datasheet 1 general description the numicro ? nuc12 1/ 125 series is a 32 - bit cortex ? - m0 microcontroller with usb 2.0 fu ll - speed device , a 1 2 - bit adc and 4 sets of 6 - channel bpwm . the nuc121 / 125 series provides the high 50 mhz operating speed, 8 kbytes sram, 8 usb endpoints and 24 channels of bpwm , which make it powerful in usb communication a nd data processing. the nuc12 1/ 125 series is ideal for industrial control, consumer electronics, and communication system applications such as printers, touch panel, gaming keyboard, gaming joystick, usb audio, pc peripherals, and alarm systems. the nuc12 1 / 125 series run s up to 50 mhz and supports 32 - bit multiplier, structure nvic (nested vector interrupt control), dual - channel apb and pdma (peripheral direct memory access) with crc function. besides, the nuc12 1/ 125 series is equipped with 3 2 kbytes fl ash memory, 8 kbytes sram, and 4 kbytes loader rom for the isp. it operates at a wide voltage range of 2.5v ~ 5.5v and temperature range of - 40 ~ +105 . it is also equipped with plenty of peripher al devices, such as 8 - channel 12 - bit ad c, usci, uart, s pi, i 2 c, i 2 s, usb 2.0 fs device , and offers low - voltage reset and brown - out detection, pwm (pulse - width modulation), capture and compare features, four sets of 32 - bit timers, watchdog timer, and internal rc oscillator. all these peripherals have b een incorporated into the nuc121 / 125 series to reduce component count, board space and system cost. additionally, the nuc12 1/ 125 series is equipped with isp (in - system programming), iap (in - application - programming) and icp (in - circuit programming) functions, which allows the user to update the program under software control through the on - chip connectivity inter face, such as swd, u art and us b . also all series support sprom. moreover, the nuc125 support voltage adjustable interface with individual i/o (1.8v - 5.5v) for saving additional cost on adjusting the interface voltage difference of peripheral components . key features support t able 1.1 * usci can be set to uart, i 2 c or spi product line usb d usci uart i 2 c spi / i 2 s timer b pwm adc nuc121 1 1 1 2 1 4 24 12 nuc125 1 1 1 2 1 4 23 11 table 1.1 - 1 key features support table the numicro ? nuc121/ 125 series is suitable for a wide range of applications such as: ? usb keyboard / mouse ? gaming - joystick ? industrial automation ? home automation ? vr peripheral application ? usb audio ? alarm system
nuc121 /125 feb . 23 , 201 7 page 10 of 150 rev 1 .0 0 nuc121 /125 series datasheet 2 features numicro ? nuc121 /125 features 2.1 ? core C arm? cortex? - m0 core running up to 50 mhz C one 24 - bit system timer C supports low power sleep mode C single - cycle 32 - bit hardware multiplier C supports programmable 4 level priorities of nested vectored interrupt controller (nvic) C supports programmable mask - able interrupts C supports serial wire debug(swd) with 2 watch - points/4 breakpoints ? built - in ldo for wide operating voltage ranged from 2.5v to 5.5v ? flash memory C supports 32 k b application rom (aprom) C supports 4 .5 kb flash for loader (ldrom) C supports 512 bytes security protection rom (sprom) C supports 12 bytes user configuration block to control system initiation C supports d ata f lash with configurable memory size C supports 512 byte s page erase for all embedded fla sh C supports in - s ystem - p rogram ming (isp) , in - a pplication - p rogram ming (iap) update embedded flash memory C supports crc - 32 checksum calculation function C supports flash all one verification function C hardware external read protection of whole flash memory by security lock bit C supports 2 - wired icp update th rough swd/ice interface ? sram memory C 8 k b embedded sram C supports byte - , half - word - and word - access C supports pdma mode ? pdma (peripheral dma) C supports 5 independent configurable channels for automatic data transfer between memories and peripherals C supports single and burst transfer type C supports normal and scatter - gather transfer modes C supports two types of priorities modes: fixed - priority and round - robin modes C supports byte - , half - word - and word - access C supports incrementing mode for the source and destinat ion address for each channel C supports time - out function for channel 0 and channel 1 C supports software and spi/i2s, uart, usci, usb, adc , pwm and timer request ? clock control C built - in 48 mhz internal high speed rc oscillator (hirc) for usb device operatio n (frequency variation < 2% at - 40oc ~ +105oc) ? dynamically calibrating the hirc osc to 48 mhz 0.25% from - 40 to 105 by external 32.768k crystal oscillator (lxt) or start of frame (sof) C built - in 10 k hz internal low speed rc oscillator for watchdog timer and wake - up operation C supports one interface to connect external crystal oscillator for high speed or low
nuc121 /125 feb . 23 , 201 7 page 11 of 150 rev 1 .0 0 nuc121 /125 series datasheet speed application ? built - in 4~24 mhz external high speed crystal oscillator (hxt) for precise timing operation ? built - in 32.768 khz external low speed crystal oscillator (lxt) for low - power system operatio n C supports one pll up to 100 mhz for high performance system operation , sourced from hirc and hxt C supports clock on - the - fly switch C supports clock failure detection for high/low speed external crystal oscillator C supports auto clock switch once clock failure detected C supports exception (nmi) generated once a clock failure detected C supports divided clock out put ? gpio C four i/o modes C ttl/schmitt trigger input selectable C i/o pin configured as interrupt source with edge/level trigger setting C supports h igh driver and high sink current i / o (up to 20 ma at 5v) C supports software selectable slew rate control C supports up to 52/38/22 gpios for lqfp64/48 and qfn33 respectively ? timer C supports 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit pre - scale counter C independent clock source for each timer C provides one - shot, periodic, toggle and continuous counting operation modes C supports event counting function to count the ev ent from external pin C supports input capture function to capture or reset counter value C supports chip wake - up from idle/power - down mode if a timer interrupt signal is generated C support timer0 ~ timer3 time - out interrupt signal or capture interrup t signal t o trigger bpwm, pwm, adc and pdma function C supports inter - timer trigger mode ? watchdog timer C supports m ultiple clock sources from lirc (default selection) , hclk/2048 and lxt C supports 8 select ions of time - out period ( 1. 6ms ~ 26 .0sec for lirc ) C supports wake u p from power - down or idle mode C supports interrupt or reset selectable on watchdog time - out ? window watchdog timer C supports m ultiple clock sources from hclk/2048 (default selection) and lirc C supports window set by 6 - bit counter with 11 - bit prescale C supports interrupt ? bpwm/capture C supports maximum clock frequency up to 100mhz C supports up to two bpwm modules, each module provides one 16 - bit counter and 6 output channels C supports independent mode for bpwm output/capture input channel C supports 12 - bit pre - scalar from 1 to 4096 C supports 16 - bit resolution bpwm counter ? up, down and up/down counter operation type C supports mask function and tri - state enable for each bpwm pin C supports interrupt on the following events:
nuc121 /125 feb . 23 , 201 7 page 12 of 150 rev 1 .0 0 nuc121 /125 series datasheet ? bpwm coun ter match zero, period value or compared v alue C supports trigger adc on the following events: ? bpwm c ounter match zero, period value or compared value C supports capture mode with 16 - bit resolution for each bpwm pin C supports rising edges, falling edges or both edges capture condition C supports input ri sing edges, falling edges or both edges capture interrupt C supports rising edges, falling edges or both edges capture with counter reload option ? pwm/capture C supports maximum clock frequency up to 100mhz C supports up to two pwm modules, each module provides three 16 - bit counter and 6 output channels C supports independent mode for pwm output/capture input channel C supports complementary mode for 3 complementary paired pwm output channel ? dead - time insertion with 12 - bit resolution ? two compared values during one period C supports 12 - bit pre - scalar from 1 to 4096 C supports 16 - bit resolution pwm counter ? up, down and up/down counter operation type C supports mask function and tri - state enable for each pwm pin C supports brake function ? brake source from pin and system safety events (clock failed, brown - out detection and cpu lockup) ? noise filter for brake source from pin ? edge detect brake source to control brake state until brake interrupt cleared ? level detect brake source to auto recover function after brake condition removed C supports interrupt on the following events: ? pwm coun ter match zero, period value or compared value ? brake condition happened C supports trigger adc on the following events: ? pwm c ounter match zero, period value or compared value C supports capture mode with 16 - bit resolution for each pwm pin C supports rising edges, falling edges or both edges capture condition C supports input rising edges, falling edges or both edges capture interrupt C supports rising edges, falling edges or both edges capture with counter reload o ption C supports pdma for capture mode ? usci C uart mode ? supports one transmit buffer and two receive buffer for data payload ? supports hardware auto flow control function ? supports programmable baud - rate generator ? support 9 - bit data transfer (support 9 - bit rs - 485) ? baud rate detection possible by built - in capture event of baud rate generator ? supports wake - up function (data and ncts wakeup only) ? supports pdma transfer C spi mode ? supports master or slave mode operation (the maximum frequency -- master = f pclk / 2 , slave = f pclk / 5) ? supports one transmit buffer and two receive buffers for data payload ? configurable bit length of a transfer word from 4 to 16 - bit ? supports msb first or lsb first transfer sequence ? supports word suspend function ? supports 3 - wire, no slave select signal, bi - direction interface
nuc121 /125 feb . 23 , 201 7 page 13 of 150 rev 1 .0 0 nuc121 /125 series datasheet ? supports wake - up function by slave select signal in slave mode ? supports one data channel half - duplex transfer ? supports pdma transfer C i 2 c mode ? full master and slave device capability ? supports of 7 - bit addressing, as well as 10 - bit addressing ? communication in standard mode (100 kbit/s) or in fast mode (up to 400 kbit/s) ? supports multi - master bus ? supports one transmit buffer and two receive buffer for data payload ? supports 10 - bit bus time - out capability ? supports bus monitor mode. ? supports power down wake - up by data toggle or address match ? supports setup/hold time programmable ? supports multiple address recognition (two slave address with mask option) ? uart C supports one set of uart C supports maximum clock frequency up to 10 mbps C full - duplex asynchronous communications C separates receive and transmit 16/16 bytes entry fifo for data payloads C supports hardware auto - flow control (rx, tx, cts and rts) C programmable receiver buffer trigger level C supports programmable baud rate ge nerator for each channel individually C supports 8 - bit receiver buffer time - out detection function C programmable transmitting data delay time between the last stop and the next start bit by setting dly (uart_tout [15:8]) C supports auto - baud rate measurement an d baud rate compensation function C supports break error, frame error, parity error and receive/transmit buffer overflow detection function C fully programmable serial - interface characteristics ? programmable number of data bit, 5 - , 6 - , 7 - , 8 - bit character ? prog rammable parity bit, even, odd, no parity or stick parity bit generation and detection ? programmable stop bit, 1, 1.5, or 2 stop bit generation C supports irda sir function mode ? supports for 3/16 bit duration for normal mode C supports lin function mode ? supports lin master/slave mode ? supports programmable break generation function for transmitter ? supports break detection function for receiver C supports rs - 485 mode ? supports rs - 485 9 - bit mode ? supports hardware or software enables to program nrts pin to contr ol rs - 485 transmission direction C supports ncts, incoming data, received data fifo reached threshold and rs - 485 address match (aad mode) wake - up function C supports pdma transfer ? spi / i 2 s C spi ? supports one set of spi controller ? supports master or slave mode operation ? configurable bit length of a transfer word from 8 to 32 - bit ? provides separate 4 - /8 - level depth transmit and receive fifo buffers
nuc121 /125 feb . 23 , 201 7 page 14 of 150 rev 1 .0 0 nuc121 /125 series datasheet ? supports msb first or lsb first transfer sequence ? supports byte reorder function ? supports pdma transfer C i 2 s ? supports master or slave mode operation ? capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes in i 2 s mode ? provides separate 4 - level depth transmit and receive fifo buffers in i 2 s mode ? supports monaural and stereo audio data in i 2 s mode ? supports pcm mode a, pcm mode b, i 2 s and msb justified data format in i 2 s mode ? supports pdma transfer ? i 2 c C supports up to two sets of i 2 c device s C supports speed up to 1mbps C supports master/slave mode C supports bidirectional data transfer between masters and slaves C supports multi - mas ter bus bus (no central master) C arbitration between simultaneously transmitting masters without corruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer C supports 14 - bit time - out counter requesting the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows C programmable clocks allow versatile rate contro l C supports multiple address recognition, four slave address with mask option C supports two - level buffer function C supports setup/hold time programmable C supports wake - up function ? usb 2.0 fs device controller C compliant with usb 2.0 full - speed specification C pro vides 1 interrupt vector with 4 different interrupt events (nevwk, vbusdet, usb and bus) C supports control/bulk/interrupt/isochronous transfer type C supports suspend function when no bus activity existing for 3 ms C supports 8 endpoints for configurable control/bulk/interrupt/isochronous transfer types and maximum 768 bytes buffer size C provides remote wake - up capability C start of frame (sof) locked clock pulse generation C supports usb 2.0 link power management (lpm) C supports crystal - less function C supports p dma transfer ? adc C supports 12 - bit sar adc C 12 - bit resolution and 10 - bit accuracy is guaranteed C analog input voltage range: 0~ av dd C up to 12 single - end analog input channels or 6 differential analog input channels C maximum adc peripheral clock frequency is 16 mhz C conversion rate up to 800k sps at 5v C configurable adc internal sampling time
nuc121 /125 feb . 23 , 201 7 page 15 of 150 rev 1 .0 0 nuc121 /125 series datasheet C supports single , burst , single - cycle scan, and continuous scan modes on enabled channels C supports individual conversion result register with valid and overrun indicators for each channel C supports digital comparator to monitor conversion result and user can select whether to generate an interrupt when conversion result matches the compare register setting C an a/d conversion can be triggered by: ? software enable ? external pin (sta dc) ? timer 0~3 overflow pulse trigger ? pwm triggers with optional start delay period C supports 2 internal channels for ? band - gap vbg input ? temperature sensor input C supports pdma transfer ? supports 96 - bit unique id (uid) ? supports 128 - bit unique customer id (ucid) ? one built - in temperature sensor with 1 resolution ? brown - out detector C with 4 levels: 4. 3 v/ 3. 7 v/ 2.7v/ 2.2v C supports brown - o ut interrupt and reset option ? low voltage reset C threshold voltage levels: 2 . 0 v ? operating temperature: - 40 ~105 ? packages C all green package (ro hs ) C lqfp 64 - pin (7mm x 7mm) C lqfp 48 - pin ( 7 mm x 7 mm) C qfn 33 - pin (5mm x 5 mm)
nuc121 /125 feb . 23 , 201 7 page 16 of 150 rev 1 .0 0 nuc121 /125 series datasheet 3 abbreviations abbreviations 3.1 acronym description acmp analog comparator controller adc analog - to - digital converter aes advanced encryption standard apb advanced peripheral bus ahb a dvanced h igh - p erformance b us bod brown - out detection dap debug access port des data encryption standard ebi external bus interface epwm enhanced pulse width modulation fifo first in, first out fmc flash memory controller fpu floating - point unit gpio general - purpose input/output hclk the clock of a dvanced h igh - p erformance b us hirc 48 mhz i nternal h igh s peed rc o scillator hxt 4~24 mhz e xternal h igh s peed c rystal o scillator iap in application programming icp in circuit programming isp in system programming ldo low dropout regulator lin local interconnect network lirc 10 khz internal low speed rc oscillator (lirc) mpu memory protection unit nvic nested vectored interrupt controller pclk the clock of advanced peripheral bus pdma peripheral direct memory access pll phase - locked loop pwm pulse width modulation qei quadrature encoder interface sd secure digital
nuc121 /125 feb . 23 , 201 7 page 17 of 150 rev 1 .0 0 nuc121 /125 series datasheet spi serial peripheral interface sps samples per second tdes triple data encryption standard tmr timer controller uart universal asynchronous receiver/transmitter ucid unique customer id usb universal serial bus wdt watchdog timer wwdt window watchdog timer table 3.1 - 1 list of abbreviations
nuc121 /125 feb . 23 , 201 7 page 18 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4 parts information li st and pin configura tion numicro ? nuc121 /125 selection guide 4.1 4.1.1 numicro ? nuc121 /125 naming rule figure 4.1 - 1 numicro ? nuc121 /125 selection code n u c a r m C ? - m 0 p r o d u c t l i n e f u n c t i o n 1 2 x - x x x x x 2 : u s b l i n e s u b - l i n e p a c k a g e t y p e z : q f n 3 3 5 x 5 m m l : l q f p 4 8 7 x 7 m m s : l q f p 6 4 7 x 7 m m t e m p e r a t u r e e : - 4 0 o c ~ + 1 0 5 o c r e s e r v e d s r a m s i z e 2 : 8 k b f l a s h r o m c : 3 2 k b 1 : w i t h o u t v d d i o 5 : w i t h v d d i o
nuc121 /125 feb . 23 , 201 7 page 19 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.1.2 numicro ? nuc121 usb series selection guide * usci can be set to uart, i 2 c or spi part number flash (kb) sram (kb) isp loader rom (kb) i/o timer /pwm connectivity pwm adc (12 - bit) pdma icp / isp /i ap 1.8v power pin package usci* uart spi /i 2 s i 2 c usb d nuc121zc 2 ae 32 8 4 .5 22 4 1 1 1 2 1 1 7 4 - ch 5 - ch nuc121lc 2 ae 32 8 4 .5 38 4 1 1 1 2 1 24 10 - ch 5 - ch nuc12 1 sc 2 ae 32 8 4 .5 52 4 1 1 1 2 1 24 1 2 - ch 5 - ch table 4.1 - 1 numicro ? nuc121 usb series selection guide 4.1.3 numicro ? nuc125 usb series selection guide * usci can be set to uart, i 2 c or spi part number flash (kb) sram (kb) isp loader rom (kb) i/o timer /pwm connectivity pwm adc (12 - bit) pdma icp / isp /i ap 1.8v power pin package usci* uart spi /i 2 s i 2 c usb d nuc12 5 zc 2 ae 32 8 4 .5 22 4 1 1 1 2 1 1 7 4 - ch 5 - ch nuc12 5 lc 2 ae 32 8 4 .5 37 4 1 1 1 2 1 2 3 10 - ch 5 - ch nuc12 5 sc 2 ae 32 8 4 .5 51 4 1 1 1 2 1 2 3 1 2 - ch 5 - ch table 4.1 - 2 numicro ? nuc125 usb series selection guide
nuc121 /125 feb . 23 , 201 7 page 20 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin configuration 4.2 4.2.1 numicro ? nuc121 qfn 33 - pin diagram figure 4.2 - 1 numicro ? nuc121 qfn 33 - pin diagram n u c 1 2 1 z q f n 3 3 3 3 v s s 1 2 3 4 5 6 7 8 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 a v d d p d . 1 p d . 2 p d . 3 p f . 0 p f . 1 n r e s e t v s s p b . 1 4 p a . 1 1 p a . 1 0 p b . 4 p b . 5 l d o _ c a p v d d v s s p c . 0 p c . 1 p c . 2 p c . 3 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s p f . 5 p f . 4 p c . 8 p c . 9 p c . 1 0 p c . 1 1 p c . 1 2 p c . 1 3 t o p t r a n s p a r e n t v i e w
nuc121 /125 feb . 23 , 201 7 page 21 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.2.2 numicro ? nuc121 qfn 33 - pin function diagram figure 4.2 - 2 numicro ? nuc121 qfn 33 - pin function diagram n u c 1 2 1 z q f n 3 3 3 3 v s s 1 2 3 4 5 6 7 8 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 a v d d s p i 0 _ c l k / u s c i 0 _ c l k / u a r t 0 _ r x d / t m 0 _ e x t / a d c _ c h 1 / p d . 1 s p i 0 _ m i s o / u s c i 0 _ d a t 1 / u a r t 0 _ t x d / t m 3 / a d c _ c h 2 / p d . 2 s p i 0 _ m o s i / u s c i 0 _ d a t 0 / u a r t 0 _ n c t s / t m 1 _ e x t / a d c _ c h 3 / p d . 3 t m 3 / b p w m 1 _ c h 3 / x t _ o u t / p f . 0 t m 1 _ e x t / b p w m 1 _ c h 2 / x t _ i n / p f . 1 n r e s e t v s s s p i 0 _ s s / b p w m 1 _ c h 0 / a d c _ c h 9 / u a r t 0 _ n r t s / i n t 0 / p b . 1 4 u s c i 0 _ d a t 0 / u s c i 0 _ c l k / t m 0 / b p w m 0 _ c h 5 / i 2 c 1 _ s c l / p a . 1 1 u s c i 0 _ d a t 1 / p w m 0 _ b r a k e 0 / b p w m 0 _ c h 4 / i 2 c 1 _ s d a / p a . 1 0 u s c i 0 _ d a t 0 / u s c i 0 _ c t l 0 / t m 2 _ e x t / b p w m 0 _ c h 3 / p b . 4 u s c i 0 _ d a t 1 / u s c i 0 _ c l k / t m 3 / b p w m 0 _ c h 2 / p b . 5 l d o _ c a p v d d v s s p c . 0 / s p i 0 _ s s / p w m 1 _ c h 0 / t m 2 / u a r t 0 _ r x d / u s c i 0 _ c l k p c . 1 / s p i 0 _ c l k / p w m 1 _ c h 1 / u a r t 0 _ t x d / u s c i 0 _ c t l 0 p c . 2 / s p i 0 _ m i s o / i 2 c 1 _ s c l / p w m 1 _ c h 2 / u a r t 0 _ n c t s / u s c i 0 _ d a t 1 p c . 3 / s p i 0 _ m o s i / i 2 c 1 _ s d a / p w m 1 _ c h 3 / u a r t 0 _ n r t s / u s c i 0 _ d a t 0 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s p f . 5 / i c e _ c l k / i 2 c 0 _ s c l / u a r t 0 _ r x d p f . 4 / i c e _ d a t / i 2 c 0 _ s d a / u a r t 0 _ t x d / p w m 0 _ c h 3 p c . 8 / s t a d c / s p i 0 _ s s / p w m 0 _ c h 4 / p w m 1 _ b r a k e 0 / u s c i 0 _ c t l 0 p c . 9 / s p i 0 _ c l k / p w m 0 _ c h 5 / p w m 0 _ b r a k e 1 / u s c i 0 _ c l k p c . 1 0 / s p i 0 _ m i s o / p w m 0 _ c h 0 / u s c i 0 _ d a t 1 p c . 1 1 / s p i 0 _ m o s i / p w m 0 _ c h 1 / t m 1 / i 2 c 0 _ s d a / u s c i 0 _ d a t 0 p c . 1 2 / p w m 0 _ c h 2 / s p i 0 _ i 2 s m c l k / c l k o / i n t 0 / i 2 c 0 _ s c l / u s c i 0 _ c t l 1 p c . 1 3 / p w m 0 _ c h 3 / c l k o / i n t 0 / i 2 c 0 _ s d a t o p t r a n s p a r e n t v i e w
nuc121 /125 feb . 23 , 201 7 page 22 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.2.3 numicro ? nuc121 lqfp 48 - pin diagram figure 4.2 - 3 numicro ? nuc121 lqfp 48 - pin diagram n u c 1 2 1 l l q f p 4 8 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 v s s p b . 8 p b . 1 4 p a . 1 1 p a . 1 0 p b . 4 p b . 5 p b . 6 p b . 7 l d o _ c a p v d d v s s p b . 9 p b . 1 0 p c . 0 p c . 1 p c . 2 p c . 3 p c . 4 p c . 5 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s p f . 5 p f . 4 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 p c . 8 p c . 9 p c . 1 0 p c . 1 1 p c . 1 2 p c . 1 3 a v d d p d . 0 p d . 1 p d . 2 p d . 3 p d . 4 p d . 5 p f . 0 p f . 1 n r e s e t p f . 2 p f . 3
nuc121 /125 feb . 23 , 201 7 page 23 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.2.4 numicro ? nuc121 lqfp 48 - pin function diagram figure 4.2 - 4 numicro ? nuc121 lqfp 48 - pin function diagram n u c 1 2 1 l l q f p 4 8 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 v s s b p w m 1 _ c h 1 / a d c _ c h 8 / t m 0 / p b . 8 s p i 0 _ s s / b p w m 1 _ c h 0 / a d c _ c h 9 / u a r t 0 _ n r t s / i n t 0 / p b . 1 4 u s c i 0 _ d a t 0 / u s c i 0 _ c l k / t m 0 / b p w m 0 _ c h 5 / i 2 c 1 _ s c l / p a . 1 1 u s c i 0 _ d a t 1 / p w m 0 _ b r a k e 0 / b p w m 0 _ c h 4 / i 2 c 1 _ s d a / p a . 1 0 u s c i 0 _ d a t 0 / u s c i 0 _ c t l 0 / t m 2 _ e x t / b p w m 0 _ c h 3 / p b . 4 u s c i 0 _ d a t 1 / u s c i 0 _ c l k / t m 3 / b p w m 0 _ c h 2 / p b . 5 u s c i 0 _ c t l 1 / u s c i 0 _ d a t 0 / b p w m 0 _ c h 1 / p b . 6 u s c i 0 _ c t l 0 / u s c i 0 _ d a t 1 / b p w m 0 _ c h 0 / p b . 7 l d o _ c a p v d d v s s p b . 9 / t m 1 / s p i 0 _ i 2 s m c l k / p w m 0 _ c h 4 p b . 1 0 / t m 2 / s p i 0 _ i 2 s m c l k / p w m 0 _ c h 5 p c . 0 / s p i 0 _ s s / p w m 1 _ c h 0 / t m 2 / u a r t 0 _ r x d / u s c i 0 _ c l k p c . 1 / s p i 0 _ c l k / p w m 1 _ c h 1 / u a r t 0 _ t x d / u s c i 0 _ c t l 0 p c . 2 / s p i 0 _ m i s o / i 2 c 1 _ s c l / p w m 1 _ c h 2 / u a r t 0 _ n c t s / u s c i 0 _ d a t 1 p c . 3 / s p i 0 _ m o s i / i 2 c 1 _ s d a / p w m 1 _ c h 3 / u a r t 0 _ n r t s / u s c i 0 _ d a t 0 p c . 4 / u a r t 0 _ r x d / s p i 0 _ i 2 s m c l k / p w m 1 _ c h 4 / u s c i 0 _ d a t 1 p c . 5 / u a r t 0 _ t x d / p w m 1 _ c h 5 / u s c i 0 _ d a t 0 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s p f . 5 / i c e _ c l k / i 2 c 0 _ s c l / u a r t 0 _ r x d p f . 4 / i c e _ d a t / i 2 c 0 _ s d a / u a r t 0 _ t x d / p w m 0 _ c h 3 p a . 1 2 / p w m 0 _ c h 0 / i 2 c 1 _ s c l / u a r t 0 _ r x d p a . 1 3 / p w m 0 _ c h 1 / i 2 c 1 _ s d a / u a r t 0 _ t x d p a . 1 4 / p w m 0 _ c h 2 / u a r t 0 _ n c t s / p w m 0 _ b r a k e 0 p a . 1 5 / p w m 0 _ c h 3 / s p i _ i 2 s m c l k / c l k o / p w m 1 _ b r a k e 1 / u a r t 0 _ n r t s p c . 8 / s t a d c / s p i 0 _ s s / p w m 0 _ c h 4 / p w m 1 _ b r a k e 0 / u s c i 0 _ c t l 0 p c . 9 / s p i 0 _ c l k / p w m 0 _ c h 5 / p w m 0 _ b r a k e 1 / u s c i 0 _ c l k p c . 1 0 / s p i 0 _ m i s o / p w m 0 _ c h 0 / u s c i 0 _ d a t 1 p c . 1 1 / s p i 0 _ m o s i / p w m 0 _ c h 1 / t m 1 / i 2 c 0 _ s d a / u s c i 0 _ d a t 0 p c . 1 2 / p w m 0 _ c h 2 / s p i 0 _ i 2 s m c l k / c l k o / i n t 0 / i 2 c 0 _ s c l / u s c i 0 _ c t l 1 p c . 1 3 / p w m 0 _ c h 3 / c l k o / i n t 0 / i 2 c 0 _ s d a a v d d s p i 0 _ s s / u s c i 0 _ c t l 0 / u a r t 0 _ n r t s / a d c _ c h 0 / p d . 0 s p i 0 _ c l k / u s c i 0 _ c l k / u a r t 0 _ r x d / t m 0 _ e x t / a d c _ c h 1 / p d . 1 s p i 0 _ m i s o / u s c i 0 _ d a t 1 / u a r t 0 _ t x d / t m 3 / a d c _ c h 2 / p d . 2 s p i 0 _ m o s i / u s c i 0 _ d a t 0 / u a r t 0 _ n c t s / t m 1 _ e x t / a d c _ c h 3 / p d . 3 s p i 0 _ s s / u s c i 0 _ c t l 0 / u a r t 0 _ n r t s / b p w m 1 _ c h 5 / a d c _ c h 4 / p d . 4 b p w m 1 _ c h 4 / a d c _ c h 5 / p d . 5 t m 3 / b p w m 1 _ c h 3 / x t _ o u t / p f . 0 t m 1 _ e x t / b p w m 1 _ c h 2 / x t _ i n / p f . 1 n r e s e t b p w m 1 _ c h 3 / a d c _ c h 6 / i 2 c 0 _ s d a / i c e _ d a t / p f . 2 b p w m 1 _ c h 2 / a d c _ c h 7 / i 2 c 0 _ s c l / i c e _ c l k / p f . 3
nuc121 /125 feb . 23 , 201 7 page 24 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.2.5 numicro ? nuc121 lqfp 64 - p in diagram figure 4.2 - 5 numicro ? nuc121 lqfp 64 - pin diagram n u c 1 2 1 s l q f p 6 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 p b . 1 4 p b . 1 3 p b . 1 2 p a . 1 1 p a . 1 0 p d . 8 p d . 9 p d . 1 0 p d . 1 1 p b . 4 p b . 5 p b . 6 p b . 7 l d o _ c a p v d d v s s p b . 9 p b . 1 0 p c . 0 p c . 1 p c . 2 p c . 3 p c . 4 p c . 5 p b . 3 p b . 2 p b . 1 p b . 0 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s a v d d p f . 5 p f . 4 p a . 1 2 p a . 1 3 p a . 1 4 p e . 0 p a . 1 5 p c . 8 p c . 9 p e . 1 p c . 1 0 p c . 1 1 p c . 1 2 p c . 1 3 p e . 2 p d . 0 p d . 1 p d . 2 p d . 3 p d . 4 p d . 5 p b . 1 5 p f . 0 p f . 1 n r e s e t v s s v d d p f . 2 p f . 3 v s s p b . 8
nuc121 /125 feb . 23 , 201 7 page 25 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.2.6 numicro ? nuc121 lqfp 64 - p in function diagram figure 4.2 - 6 numicro ? nuc121 lqfp 64 - pin function diagram n u c 1 2 1 s l q f p 6 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 s p i 0 _ s s / b p w m 1 _ c h 0 / a d c _ c h 9 / u a r t 0 _ n r t s / i n t 0 / p b . 1 4 u s c i 0 _ c t l 1 / a d c _ c h 1 0 / p b . 1 3 u s c i 0 _ c t l 0 / a d c _ c h 1 1 / c l k o / p b . 1 2 u s c i 0 _ d a t 0 / u s c i 0 _ c l k / t m 0 / b p w m 0 _ c h 5 / i 2 c 1 _ s c l / p a . 1 1 u s c i 0 _ d a t 1 / p w m 0 _ b r a k e 0 / b p w m 0 _ c h 4 / i 2 c 1 _ s d a / p a . 1 0 u s c i 0 _ d a t 0 / p d . 8 p w m 0 _ b r a k e 1 / p d . 9 b p w m 0 _ c h 5 / c l k o / p d . 1 0 b p w m 0 _ c h 4 / i n t 1 / p d . 1 1 u s c i 0 _ d a t 0 / u s c i 0 _ c t l 0 / t m 2 _ e x t / b p w m 0 _ c h 3 / p b . 4 u s c i 0 _ d a t 1 / u s c i 0 _ c l k / t m 3 / b p w m 0 _ c h 2 / p b . 5 u s c i 0 _ c t l 1 / u s c i 0 _ d a t 0 / b p w m 0 _ c h 1 / p b . 6 u s c i 0 _ c t l 0 / u s c i 0 _ d a t 1 / b p w m 0 _ c h 0 / p b . 7 l d o _ c a p v d d v s s p b . 9 / t m 1 / s p i 0 _ i 2 s m c l k / p w m 0 _ c h 4 p b . 1 0 / t m 2 / s p i 0 _ i 2 s m c l k / p w m 0 _ c h 5 p c . 0 / s p i 0 _ s s / p w m 1 _ c h 0 / t m 2 / u a r t 0 _ r x d / u s c i 0 _ c l k p c . 1 / s p i 0 _ c l k / p w m 1 _ c h 1 / u a r t 0 _ t x d / u s c i 0 _ c t l 0 p c . 2 / s p i 0 _ m i s o / i 2 c 1 _ s c l / p w m 1 _ c h 2 / u a r t 0 _ n c t s / u s c i 0 _ d a t 1 p c . 3 / s p i 0 _ m o s i / i 2 c 1 _ s d a / p w m 1 _ c h 3 / u a r t 0 _ n r t s / u s c i 0 _ d a t 0 p c . 4 / u a r t 0 _ r x d / s p i 0 _ i 2 s m c l k / p w m 1 _ c h 4 / u s c i 0 _ d a t 1 p c . 5 / u a r t 0 _ t x d / p w m 1 _ c h 5 / u s c i 0 _ d a t 0 p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t / p w m 1 _ c h 3 p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t / p w m 1 _ c h 2 p b . 1 / u a r t 0 _ t x d / p w m 1 _ c h 1 p b . 0 / u a r t 0 _ r x d / p w m 1 _ c h 0 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s a v d d p f . 5 / i c e _ c l k / i 2 c 0 _ s c l / u a r t 0 _ r x d p f . 4 / i c e _ d a t / i 2 c 0 _ s d a / u a r t 0 _ t x d / p w m 0 _ c h 3 p a . 1 2 / p w m 0 _ c h 0 / i 2 c 1 _ s c l / u a r t 0 _ r x d p a . 1 3 / p w m 0 _ c h 1 / i 2 c 1 _ s d a / u a r t 0 _ t x d p a . 1 4 / p w m 0 _ c h 2 / u a r t 0 _ n c t s / p w m 0 _ b r a k e 0 p e . 0 / i n t 0 / c l k o / p w m 0 _ c h 3 / t m 1 _ e x t / u s c i 0 _ d a t 0 p a . 1 5 / p w m 0 _ c h 3 / s p i _ i 2 s m c l k / c l k o / p w m 1 _ b r a k e 1 / u a r t 0 _ n r t s p c . 8 / s t a d c / s p i 0 _ s s / p w m 0 _ c h 4 / p w m 1 _ b r a k e 0 / u s c i 0 _ c t l 0 p c . 9 / s p i 0 _ c l k / p w m 0 _ c h 5 / p w m 0 _ b r a k e 1 / u s c i 0 _ c l k p e . 1 / s t a d c / c l k o / t m 3 / u s c i 0 _ d a t 1 p c . 1 0 / s p i 0 _ m i s o / p w m 0 _ c h 0 / u s c i 0 _ d a t 1 p c . 1 1 / s p i 0 _ m o s i / p w m 0 _ c h 1 / t m 1 / i 2 c 0 _ s d a / u s c i 0 _ d a t 0 p c . 1 2 / p w m 0 _ c h 2 / s p i 0 _ i 2 s m c l k / c l k o / i n t 0 / i 2 c 0 _ s c l / u s c i 0 _ c t l 1 p c . 1 3 / p w m 0 _ c h 3 / c l k o / i n t 0 / i 2 c 0 _ s d a p e . 2 / i n t 1 / t m 0 _ e x t / i 2 c 0 _ s c l / u s c i 0 _ c t l 1 s p i 0 _ s s / u s c i 0 _ c t l 0 / u a r t 0 _ n r t s / a d c _ c h 0 / p d . 0 s p i 0 _ c l k / u s c i 0 _ c l k / u a r t 0 _ r x d / t m 0 _ e x t / a d c _ c h 1 / p d . 1 s p i 0 _ m i s o / u s c i 0 _ d a t 1 / u a r t 0 _ t x d / t m 3 / a d c _ c h 2 / p d . 2 s p i 0 _ m o s i / u s c i 0 _ d a t 0 / u a r t 0 _ n c t s / t m 1 _ e x t / a d c _ c h 3 / p d . 3 s p i 0 _ s s / u s c i 0 _ c t l 0 / u a r t 0 _ n r t s / b p w m 1 _ c h 5 / a d c _ c h 4 / p d . 4 b p w m 1 _ c h 4 / a d c _ c h 5 / p d . 5 b p w m 1 _ c h 5 / t m 0 _ e x t / i n t 1 / p b . 1 5 t m 3 / b p w m 1 _ c h 3 / x t _ o u t / p f . 0 t m 1 _ e x t / b p w m 1 _ c h 2 / x t _ i n / p f . 1 n r e s e t v s s v d d b p w m 1 _ c h 3 / a d c _ c h 6 / i 2 c 0 _ s d a / i c e _ d a t / p f . 2 b p w m 1 _ c h 2 / a d c _ c h 7 / i 2 c 0 _ s c l / i c e _ c l k / p f . 3 v s s b p w m 1 _ c h 1 / a d c _ c h 8 / t m 0 / p b . 8
nuc121 /125 feb . 23 , 201 7 page 26 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.2.7 numicro ? nuc125 qfn 33 - pin diagram figure 4.2 - 7 numicro ? nuc125 qfn 33 - pin diagram n u c 1 2 5 z q f n 3 3 3 3 v s s 1 2 3 4 5 6 7 8 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 a v d d p d . 1 p d . 2 p d . 3 p f . 0 p f . 1 n r e s e t v d d i o p b . 1 4 p a . 1 1 p a . 1 0 p b . 4 p b . 5 l d o _ c a p v d d v s s p c . 0 p c . 1 p c . 2 p c . 3 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s p f . 5 p f . 4 p c . 8 p c . 9 p c . 1 0 p c . 1 1 p c . 1 2 p c . 1 3 t o p t r a n s p a r e n t v i e w v d d i o p o w e r d o m a i n
nuc121 /125 feb . 23 , 201 7 page 27 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.2.8 numicro ? nuc125 qfn 33 - pin function diagram figure 4.2 - 8 numicro ? nuc125 qfn 33 - pin function diagram n u c 1 2 5 z q f n 3 3 3 3 v s s 1 2 3 4 5 6 7 8 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 a v d d s p i 0 _ c l k / u s c i 0 _ c l k / u a r t 0 _ r x d / t m 0 _ e x t / a d c _ c h 1 / p d . 1 s p i 0 _ m i s o / u s c i 0 _ d a t 1 / u a r t 0 _ t x d / t m 3 / a d c _ c h 2 / p d . 2 s p i 0 _ m o s i / u s c i 0 _ d a t 0 / u a r t 0 _ n c t s / t m 1 _ e x t / a d c _ c h 3 / p d . 3 t m 3 / b p w m 1 _ c h 3 / x t _ o u t / p f . 0 t m 1 _ e x t / b p w m 1 _ c h 2 / x t _ i n / p f . 1 n r e s e t v d d i o s p i 0 _ s s / b p w m 1 _ c h 0 / a d c _ c h 9 / u a r t 0 _ n r t s / i n t 0 / p b . 1 4 u s c i 0 _ d a t 0 / u s c i 0 _ c l k / t m 0 / b p w m 0 _ c h 5 / i 2 c 1 _ s c l / p a . 1 1 u s c i 0 _ d a t 1 / p w m 0 _ b r a k e 0 / b p w m 0 _ c h 4 / i 2 c 1 _ s d a / p a . 1 0 u s c i 0 _ d a t 0 / u s c i 0 _ c t l 0 / t m 2 _ e x t / b p w m 0 _ c h 3 / p b . 4 u s c i 0 _ d a t 1 / u s c i 0 _ c l k / t m 3 / b p w m 0 _ c h 2 / p b . 5 l d o _ c a p v d d v s s p c . 0 / s p i 0 _ s s / p w m 1 _ c h 0 / t m 2 / u a r t 0 _ r x d / u s c i 0 _ c l k p c . 1 / s p i 0 _ c l k / p w m 1 _ c h 1 / u a r t 0 _ t x d / u s c i 0 _ c t l 0 p c . 2 / s p i 0 _ m i s o / i 2 c 1 _ s c l / p w m 1 _ c h 2 / u a r t 0 _ n c t s / u s c i 0 _ d a t 1 p c . 3 / s p i 0 _ m o s i / i 2 c 1 _ s d a / p w m 1 _ c h 3 / u a r t 0 _ n r t s / u s c i 0 _ d a t 0 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s p f . 5 / i c e _ c l k / i 2 c 0 _ s c l / u a r t 0 _ r x d p f . 4 / i c e _ d a t / i 2 c 0 _ s d a / u a r t 0 _ t x d / p w m 0 _ c h 3 p c . 8 / s t a d c / s p i 0 _ s s / p w m 0 _ c h 4 / p w m 1 _ b r a k e 0 / u s c i 0 _ c t l 0 p c . 9 / s p i 0 _ c l k / p w m 0 _ c h 5 / p w m 0 _ b r a k e 1 / u s c i 0 _ c l k p c . 1 0 / s p i 0 _ m i s o / p w m 0 _ c h 0 / u s c i 0 _ d a t 1 p c . 1 1 / s p i 0 _ m o s i / p w m 0 _ c h 1 / t m 1 / i 2 c 0 _ s d a / u s c i 0 _ d a t 0 p c . 1 2 / p w m 0 _ c h 2 / s p i 0 _ i 2 s m c l k / c l k o / i n t 0 / i 2 c 0 _ s c l / u s c i 0 _ c t l 1 p c . 1 3 / p w m 0 _ c h 3 / c l k o / i n t 0 / i 2 c 0 _ s d a t o p t r a n s p a r e n t v i e w v d d i o p o w e r d o m a i n
nuc121 /125 feb . 23 , 201 7 page 28 of 1 50 rev 1 .0 0 nuc121 /125 series datasheet 4.2.9 numicro ? nuc125 lqfp 48 - pin diagram figure 4.2 - 9 numicro ? nuc125 lqfp 48 - pin diagram n u c 1 2 5 l l q f p 4 8 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 v s s v d d i o p b . 1 4 p a . 1 1 p a . 1 0 p b . 4 p b . 5 p b . 6 p b . 7 l d o _ c a p v d d v s s p b . 9 p b . 1 0 p c . 0 p c . 1 p c . 2 p c . 3 p c . 4 p c . 5 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s p f . 5 p f . 4 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 p c . 8 p c . 9 p c . 1 0 p c . 1 1 p c . 1 2 p c . 1 3 a v d d p d . 0 p d . 1 p d . 2 p d . 3 p d . 4 p d . 5 p f . 0 p f . 1 n r e s e t p f . 2 p f . 3 v d d i o p o w e r d o m a i n
nuc121 /125 feb . 23 , 201 7 page 29 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.2.10 numicro ? nuc125 lqfp 48 - pin function diagram figure 4.2 - 10 numicro ? nuc125 lqfp 48 - pin function diagram n u c 1 2 5 l l q f p 4 8 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 v s s v d d i o s p i 0 _ s s / b p w m 1 _ c h 0 / a d c _ c h 9 / u a r t 0 _ n r t s / i n t 0 / p b . 1 4 u s c i 0 _ d a t 0 / u s c i 0 _ c l k / t m 0 / b p w m 0 _ c h 5 / i 2 c 1 _ s c l / p a . 1 1 u s c i 0 _ d a t 1 / p w m 0 _ b r a k e 0 / b p w m 0 _ c h 4 / i 2 c 1 _ s d a / p a . 1 0 u s c i 0 _ d a t 0 / u s c i 0 _ c t l 0 / t m 2 _ e x t / b p w m 0 _ c h 3 / p b . 4 u s c i 0 _ d a t 1 / u s c i 0 _ c l k / t m 3 / b p w m 0 _ c h 2 / p b . 5 u s c i 0 _ c t l 1 / u s c i 0 _ d a t 0 / b p w m 0 _ c h 1 / p b . 6 u s c i 0 _ c t l 0 / u s c i 0 _ d a t 1 / b p w m 0 _ c h 0 / p b . 7 l d o _ c a p v d d v s s p b . 9 / t m 1 / s p i 0 _ i 2 s m c l k / p w m 0 _ c h 4 p b . 1 0 / t m 2 / s p i 0 _ i 2 s m c l k / p w m 0 _ c h 5 p c . 0 / s p i 0 _ s s / p w m 1 _ c h 0 / t m 2 / u a r t 0 _ r x d / u s c i 0 _ c l k p c . 1 / s p i 0 _ c l k / p w m 1 _ c h 1 / u a r t 0 _ t x d / u s c i 0 _ c t l 0 p c . 2 / s p i 0 _ m i s o / i 2 c 1 _ s c l / p w m 1 _ c h 2 / u a r t 0 _ n c t s / u s c i 0 _ d a t 1 p c . 3 / s p i 0 _ m o s i / i 2 c 1 _ s d a / p w m 1 _ c h 3 / u a r t 0 _ n r t s / u s c i 0 _ d a t 0 p c . 4 / u a r t 0 _ r x d / s p i 0 _ i 2 s m c l k / p w m 1 _ c h 4 / u s c i 0 _ d a t 1 p c . 5 / u a r t 0 _ t x d / p w m 1 _ c h 5 / u s c i 0 _ d a t 0 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s p f . 5 / i c e _ c l k / i 2 c 0 _ s c l / u a r t 0 _ r x d p f . 4 / i c e _ d a t / i 2 c 0 _ s d a / u a r t 0 _ t x d / p w m 0 _ c h 3 p a . 1 2 / p w m 0 _ c h 0 / i 2 c 1 _ s c l / u a r t 0 _ r x d p a . 1 3 / p w m 0 _ c h 1 / i 2 c 1 _ s d a / u a r t 0 _ t x d p a . 1 4 / p w m 0 _ c h 2 / u a r t 0 _ n c t s / p w m 0 _ b r a k e 0 p a . 1 5 / p w m 0 _ c h 3 / s p i _ i 2 s m c l k / c l k o / p w m 1 _ b r a k e 1 / u a r t 0 _ n r t s p c . 8 / s t a d c / s p i 0 _ s s / p w m 0 _ c h 4 / p w m 1 _ b r a k e 0 / u s c i 0 _ c t l 0 p c . 9 / s p i 0 _ c l k / p w m 0 _ c h 5 / p w m 0 _ b r a k e 1 / u s c i 0 _ c l k p c . 1 0 / s p i 0 _ m i s o / p w m 0 _ c h 0 / u s c i 0 _ d a t 1 p c . 1 1 / s p i 0 _ m o s i / p w m 0 _ c h 1 / t m 1 / i 2 c 0 _ s d a / u s c i 0 _ d a t 0 p c . 1 2 / p w m 0 _ c h 2 / s p i 0 _ i 2 s m c l k / c l k o / i n t 0 / i 2 c 0 _ s c l / u s c i 0 _ c t l 1 p c . 1 3 / p w m 0 _ c h 3 / c l k o / i n t 0 / i 2 c 0 _ s d a a v d d s p i 0 _ s s / u s c i 0 _ c t l 0 / u a r t 0 _ n r t s / a d c _ c h 0 / p d . 0 s p i 0 _ c l k / u s c i 0 _ c l k / u a r t 0 _ r x d / t m 0 _ e x t / a d c _ c h 1 / p d . 1 s p i 0 _ m i s o / u s c i 0 _ d a t 1 / u a r t 0 _ t x d / t m 3 / a d c _ c h 2 / p d . 2 s p i 0 _ m o s i / u s c i 0 _ d a t 0 / u a r t 0 _ n c t s / t m 1 _ e x t / a d c _ c h 3 / p d . 3 s p i 0 _ s s / u s c i 0 _ c t l 0 / u a r t 0 _ n r t s / b p w m 1 _ c h 5 / a d c _ c h 4 / p d . 4 b p w m 1 _ c h 4 / a d c _ c h 5 / p d . 5 t m 3 / b p w m 1 _ c h 3 / x t _ o u t / p f . 0 t m 1 _ e x t / b p w m 1 _ c h 2 / x t _ i n / p f . 1 n r e s e t b p w m 1 _ c h 3 / a d c _ c h 6 / i 2 c 0 _ s d a / i c e _ d a t / p f . 2 b p w m 1 _ c h 2 / a d c _ c h 7 / i 2 c 0 _ s c l / i c e _ c l k / p f . 3 v d d i o p o w e r d o m a i n
nuc121 /125 feb . 23 , 201 7 page 30 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.2.11 numicro ? nuc125 lqfp 64 - p in diagram figure 4.2 - 11 numicro ? nuc125 lqfp 64 - pin diagram n u c 1 2 5 s l q f p 6 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 p b . 1 4 p b . 1 3 p b . 1 2 p a . 1 1 p a . 1 0 p d . 8 p d . 9 p d . 1 0 p d . 1 1 p b . 4 p b . 5 p b . 6 p b . 7 l d o _ c a p v d d v s s p b . 9 p b . 1 0 p c . 0 p c . 1 p c . 2 p c . 3 p c . 4 p c . 5 p b . 3 p b . 2 p b . 1 p b . 0 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s a v d d p f . 5 p f . 4 p a . 1 2 p a . 1 3 p a . 1 4 p e . 0 p a . 1 5 p c . 8 p c . 9 p e . 1 p c . 1 0 p c . 1 1 p c . 1 2 p c . 1 3 p e . 2 p d . 0 p d . 1 p d . 2 p d . 3 p d . 4 p d . 5 p b . 1 5 p f . 0 p f . 1 n r e s e t v s s v d d p f . 2 p f . 3 v s s v d d i o v d d i o p o w e r d o m a i n
nuc121 /125 feb . 23 , 201 7 page 31 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.2.12 numicro ? nuc125 lqfp 64 - p in function diagram figure 4.2 - 12 numicro ? nuc125 lqfp 64 - pin function diagram n u c 1 2 5 s l q f p 6 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 s p i 0 _ s s / b p w m 1 _ c h 0 / a d c _ c h 9 / u a r t 0 _ n r t s / i n t 0 / p b . 1 4 u s c i 0 _ c t l 1 / a d c _ c h 1 0 / p b . 1 3 u s c i 0 _ c t l 0 / a d c _ c h 1 1 / c l k o / p b . 1 2 u s c i 0 _ d a t 0 / u s c i 0 _ c l k / t m 0 / b p w m 0 _ c h 5 / i 2 c 1 _ s c l / p a . 1 1 u s c i 0 _ d a t 1 / p w m 0 _ b r a k e 0 / b p w m 0 _ c h 4 / i 2 c 1 _ s d a / p a . 1 0 u s c i 0 _ d a t 0 / p d . 8 p w m 0 _ b r a k e 1 / p d . 9 b p w m 0 _ c h 5 / c l k o / p d . 1 0 b p w m 0 _ c h 4 / i n t 1 / p d . 1 1 u s c i 0 _ d a t 0 / u s c i 0 _ c t l 0 / t m 2 _ e x t / b p w m 0 _ c h 3 / p b . 4 u s c i 0 _ d a t 1 / u s c i 0 _ c l k / t m 3 / b p w m 0 _ c h 2 / p b . 5 u s c i 0 _ c t l 1 / u s c i 0 _ d a t 0 / b p w m 0 _ c h 1 / p b . 6 u s c i 0 _ c t l 0 / u s c i 0 _ d a t 1 / b p w m 0 _ c h 0 / p b . 7 l d o _ c a p v d d v s s p b . 9 / t m 1 / s p i 0 _ i 2 s m c l k / p w m 0 _ c h 4 p b . 1 0 / t m 2 / s p i 0 _ i 2 s m c l k / p w m 0 _ c h 5 p c . 0 / s p i 0 _ s s / p w m 1 _ c h 0 / t m 2 / u a r t 0 _ r x d / u s c i 0 _ c l k p c . 1 / s p i 0 _ c l k / p w m 1 _ c h 1 / u a r t 0 _ t x d / u s c i 0 _ c t l 0 p c . 2 / s p i 0 _ m i s o / i 2 c 1 _ s c l / p w m 1 _ c h 2 / u a r t 0 _ n c t s / u s c i 0 _ d a t 1 p c . 3 / s p i 0 _ m o s i / i 2 c 1 _ s d a / p w m 1 _ c h 3 / u a r t 0 _ n r t s / u s c i 0 _ d a t 0 p c . 4 / u a r t 0 _ r x d / s p i 0 _ i 2 s m c l k / p w m 1 _ c h 4 / u s c i 0 _ d a t 1 p c . 5 / u a r t 0 _ t x d / p w m 1 _ c h 5 / u s c i 0 _ d a t 0 p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t / p w m 1 _ c h 3 p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t / p w m 1 _ c h 2 p b . 1 / u a r t 0 _ t x d / p w m 1 _ c h 1 p b . 0 / u a r t 0 _ r x d / p w m 1 _ c h 0 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s a v d d p f . 5 / i c e _ c l k / i 2 c 0 _ s c l / u a r t 0 _ r x d p f . 4 / i c e _ d a t / i 2 c 0 _ s d a / u a r t 0 _ t x d / p w m 0 _ c h 3 p a . 1 2 / p w m 0 _ c h 0 / i 2 c 1 _ s c l / u a r t 0 _ r x d p a . 1 3 / p w m 0 _ c h 1 / i 2 c 1 _ s d a / u a r t 0 _ t x d p a . 1 4 / p w m 0 _ c h 2 / u a r t 0 _ n c t s / p w m 0 _ b r a k e 0 p e . 0 / i n t 0 / c l k o / p w m 0 _ c h 3 / t m 1 _ e x t / u s c i 0 _ d a t 0 p a . 1 5 / p w m 0 _ c h 3 / s p i _ i 2 s m c l k / c l k o / p w m 1 _ b r a k e 1 / u a r t 0 _ n r t s p c . 8 / s t a d c / s p i 0 _ s s / p w m 0 _ c h 4 / p w m 1 _ b r a k e 0 / u s c i 0 _ c t l 0 p c . 9 / s p i 0 _ c l k / p w m 0 _ c h 5 / p w m 0 _ b r a k e 1 / u s c i 0 _ c l k p e . 1 / s t a d c / c l k o / t m 3 / u s c i 0 _ d a t 1 p c . 1 0 / s p i 0 _ m i s o / p w m 0 _ c h 0 / u s c i 0 _ d a t 1 p c . 1 1 / s p i 0 _ m o s i / p w m 0 _ c h 1 / t m 1 / i 2 c 0 _ s d a / u s c i 0 _ d a t 0 p c . 1 2 / p w m 0 _ c h 2 / s p i 0 _ i 2 s m c l k / c l k o / i n t 0 / i 2 c 0 _ s c l / u s c i 0 _ c t l 1 p c . 1 3 / p w m 0 _ c h 3 / c l k o / i n t 0 / i 2 c 0 _ s d a p e . 2 / i n t 1 / t m 0 _ e x t / i 2 c 0 _ s c l / u s c i 0 _ c t l 1 s p i 0 _ s s / u s c i 0 _ c t l 0 / u a r t 0 _ n r t s / a d c _ c h 0 / p d . 0 s p i 0 _ c l k / u s c i 0 _ c l k / u a r t 0 _ r x d / t m 0 _ e x t / a d c _ c h 1 / p d . 1 s p i 0 _ m i s o / u s c i 0 _ d a t 1 / u a r t 0 _ t x d / t m 3 / a d c _ c h 2 / p d . 2 s p i 0 _ m o s i / u s c i 0 _ d a t 0 / u a r t 0 _ n c t s / t m 1 _ e x t / a d c _ c h 3 / p d . 3 s p i 0 _ s s / u s c i 0 _ c t l 0 / u a r t 0 _ n r t s / b p w m 1 _ c h 5 / a d c _ c h 4 / p d . 4 b p w m 1 _ c h 4 / a d c _ c h 5 / p d . 5 b p w m 1 _ c h 5 / t m 0 _ e x t / i n t 1 / p b . 1 5 t m 3 / b p w m 1 _ c h 3 / x t _ o u t / p f . 0 t m 1 _ e x t / b p w m 1 _ c h 2 / x t _ i n / p f . 1 n r e s e t v s s v d d b p w m 1 _ c h 3 / a d c _ c h 6 / i 2 c 0 _ s d a / i c e _ d a t / p f . 2 b p w m 1 _ c h 2 / a d c _ c h 7 / i 2 c 0 _ s c l / i c e _ c l k / p f . 3 v s s v d d i o v d d i o p o w e r d o m a i n
nuc121 /125 feb . 23 , 201 7 page 32 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin description 4.3 4.3.1 nuc121 usb series qfn33 pin description mfp* = multi - function pin. (ref er to section sys_gpx_mfpl and sys_gpx_mfph) pa.10 mfp5 means sys_gpa_mfph[11:8]=0x5. pc.0 mfp0 means sys_gpc_mfpl[3:0]=0x0. pin no. pin name type mfp * description 1 pb.14 i/o mfp0 general purpose digital i/o pin. int0 i mfp1 external interrupt0 input pin. uart0_ n rts o mfp2 request to send output pin for uart 0. adc_ch9 a mfp3 adc channel 9 analog input. bpwm1_ch0 i/o mfp4 bpwm1 channel 0 output/capture input. spi0_ss i/o mfp7 spi0 slave select pin. 2 pa.11 i/o mfp0 general purpose digital i/o pin. i2c1_scl i/o mfp1 i 2 c1 clock pin. bpwm0_ch5 i/o mfp4 bpwm0 channel 5 output/capture input. tm0 i/o mfp5 timer0event counter input / toggle output usci0 _clk i/o mfp6 usci0 clock pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 3 pa.10 i/o mfp0 general purpose digital i/o pin. i2c1_sda i/o mfp1 i 2 c1 data input/output pin. bpwm0_ch4 i/o mfp4 bpwm0 channel 4 output/capture input. pwm0_brake0 i mfp5 brake input pin 0 of pwm0. usci0 _dat1 i/o mfp6 usci0 dat1 pin. 4 pb.4 i/o mfp0 general purpose digital i/o pin. bpwm0_ch3 i/o mfp4 bpwm0 channel 3 output/capture input. tm2_ext i mfp5 timer2 external counter input usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 5 pb.5 i/o mfp0 general purpose digital i/o pin. bpwm0_ch2 i/o mfp4 bpwm0 channel 2 output/capture input. tm3 i/o mfp5 timer3 event counter input / toggle output usci0 _clk i/o mfp6 usci0 clock pin. usci0 _dat1 i/o mfp7 usci0 dat1 pin.
nuc121 /125 feb . 23 , 201 7 page 33 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description 6 ldo_cap a mfp0 ldo output pin. 7 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 8 v ss a mfp0 ground pin for digital circuit. 9 usb_vbus a mfp0 power supply from usb host or hub. 10 usb_vdd33_cap a mfp0 internal power regulator output 3.3v decoupling pin. 11 usb_d - i mfp0 usb differential signal d - . 12 usb_d+ i mfp0 usb differential signal d+. 13 pc.3 i/o mfp0 general purpose digital i/o pin. spi0_mosi i/o mfp1 spi0 mosi (master out, slave in) pin. i2c1_sda i/o mfp3 i 2 c1 data input/output pin. pwm1_ch3 i/o mfp4 pwm1 channel3 output/capture input. uart0_ n rts o mfp6 request to send output pin for uart 0 . usci0 _dat0 i/o mfp7 usci0 dat0 pin. 14 pc.2 i/o mfp0 general purpose digital i/o pin. spi0_miso i/o mfp1 spi0 miso (master in, slave out) pin. i2c1_scl i/o mfp3 i 2 c1 clock pin. pwm1_ch2 i/o mfp4 pwm1 channel2 output/capture input. uart0_ n cts i mfp6 clear to send input pin for uart0. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 15 pc.1 i/o mfp0 general purpose digital i/o pin. spi0_clk i/o mfp1 spi0 serial clock pin. pwm1_ch1 i/o mfp4 pwm1 channel1 output/capture input. uart0_txd o mfp6 data transmitter output pin for uart0. usci0 _ctl0 i/o mfp7 usci0 ctl0 pin 16 pc.0 i/o mfp0 general purpose digital i/o pin. spi0_ss i/o mfp1 spi0 slave select pin. pwm1_ch0 i/o mfp4 pwm1 channel0 output/capture input. tm2 i/o mfp5 timer2 event counter input / toggle output uart0_rxd i mfp6 data receiver input pin for uart0. usci0 _clk i/o mfp7 usci0 clock pin. 17 pc.13 i/o mfp0 general purpose digital i/o pin. pwm0_ch3 i/o mfp2 pwm0 channel3 output/capture input. clko o mfp3 clock out
nuc121 /125 feb . 23 , 201 7 page 34 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description int0 i mfp5 external interrupt0 input pin. i2c0_sda i/o mfp6 i 2 c0 data input/output pin. 18 pc.12 i/o mfp0 general purpose digital i/o pin. pwm0_ch2 i/o mfp2 pwm0 channel2 output/capture input. spi0_i2smclk o mfp3 i2s0 master clock output pin. clko o mfp4 clock out int0 i mfp5 external interrupt0 input pin. i2c0_scl i/o mfp6 i 2 c0 clock pin. usci0 _ctl1 i/o mfp7 usci0 ctl1 pin. 19 pc.11 i/o mfp0 general purpose digital i/o pin. spi0_mosi i/o mfp3 spi0 mosi (master out, slave in) pin. pwm0_ch1 i/o mfp4 pwm0 channel1 output/capture input. tm1 i/o mfp5 timer1 event counter input / toggle output i2c0_sda i/o mfp6 i 2 c0 data input/output pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 20 pc.10 i/o mfp0 general purpose digital i/o pin. spi0_miso i/o mfp3 spi0 miso (master in, slave out) pin. pwm0_ch0 i/o mfp4 pwm0 channel0 output/capture input. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 21 pc.9 i/o mfp0 general purpose digital i/o pin. spi0_clk i/o mfp3 spi0 serial clock pin. pwm0_ch5 i/o mfp4 pwm0 channel5 output/capture input. pwm0_brake1 i mfp5 brake input pin 1 of pwm 0 . usci0 _clk i/o mfp7 usci0 clock pin 22 pc.8 i/o mfp0 general purpose digital i/o pin. stadc i mfp2 adc external trigger input. spi0_ss i/o mfp3 spi0 slave select pin. pwm0_ch4 i/o mfp4 pwm0 channel4 output/capture input. pwm1_brake0 i mfp5 brake input pin 0 of pwm 1 . usci0 _ctl0 i/o mfp7 usci0 ctl0 pin 23 pf.4 i/o mfp0 general purpose digital i/o pin. ice_dat i/o mfp1 serial wired debugger data pin i2c0_sda i/o mfp2 i 2 c0 data input/output pin.
nuc121 /125 feb . 23 , 201 7 page 35 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description uart0_txd o mfp3 data transmitter output pin for uart0. pwm0_ch3 i/o mfp4 pwm0 channel3 output/capture input. 24 pf.5 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin i2c0_scl i/o mfp2 i 2 c0 clock pin. uart0_rxd i mfp3 data receiver input pin for uart0. 25 av dd a mfp0 power supply for internal analog circuit. 26 pd.1 i/o mfp0 general purpose digital i/o pin. adc_ch1 a mfp3 adc channel 1 analog input. tm0_ext i mfp4 timer0 external counter input uart0_rxd i mfp5 data receiver input pin for uart0. usci0 _clk i/o mfp6 usci0 clock pin. spi0_clk i/o mfp7 spi0 serial clock pin. 27 pd.2 i/o mfp0 general purpose digital i/o pin. adc_ch2 a mfp3 adc channel 2 analog input. tm3 i/o mfp4 timer3 event counter input / toggle output uart0_txd o mfp5 data transmitter output pin for uart0. usci0 _dat1 i/o mfp6 usci0 dat1 pin. spi0_miso i/o mfp7 spi0 miso (master in, slave out) pin. 28 pd.3 i/o mfp0 general purpose digital i/o pin. adc_ch3 a mfp3 adc channel 3 analog input. tm1_ext i mfp4 timer1 external counter input uart0_ n cts i mfp5 clear to send input pin for uart0. usci0 _dat0 i/o mfp6 usci0 dat0 pin. spi0_mosi i/o mfp7 spi0 mosi (master out, slave in) pin. 29 pf.0 i/o mfp0 general purpose digital i/o pin. xt_out o mfp1 external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal output pin. bpwm1_ch3 i/o mfp4 bpwm1 channel 3 output/capture input. tm3 i/o mfp5 timer3 event counter input / toggle output 30 pf.1 i/o mfp0 general purpose digital i/o pin. xt_in i mfp1 external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal input pin. bpwm1_ch2 i/o mfp4 bpwm1 channel 2 output/capture input.
nuc121 /125 feb . 23 , 201 7 page 36 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description tm1_ext i mfp5 timer1 external counter input 31 nreset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 32 v ss a mfp0 ground pin for digital circuit. 3 3 v ss a mfp0 ground pin for digital circuit. table 4.3 - 1 nuc121 usb series qfn33 pin description
nuc121 /125 feb . 23 , 201 7 page 37 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.3.2 nuc121 usb series lqfp48 pin description mfp* = multi - function pin. (ref er to section sys_gpx_mfpl and sys_gpx_mfph) pa.10 mfp5 means sys_gpa_mfph[11:8]=0x5. pc.0 mfp0 means sys_gpc_mfpl[3:0]=0x0.. pin no. pin name type mfp * description 1 v ss a mfp0 ground pin for digital circuit. 2 pb.8 i/o mfp0 general purpose digital i/o pin. tm0 i/o mfp1 timer0event counter input / toggle output adc_ch8 a mfp3 adc channel 8 analog input. bpwm1_ch1 i/o mfp4 bpwm1 channel 1 output/capture input. 3 pb.14 i/o mfp0 general purpose digital i/o pin. int0 i mfp1 external interrupt0 input pin. uart0_ n rts o mfp2 request to send output pin for uart 0. adc_ch9 a mfp3 adc channel 9 analog input. bpwm1_ch0 i/o mfp4 bpwm1 channel 0 output/capture input. spi0_ss i/o mfp7 spi0 slave select pin. 4 pa.11 i/o mfp0 general purpose digital i/o pin. i2c1_scl i/o mfp1 i 2 c1 clock pin. bpwm0_ch5 i/o mfp4 bpwm0 channel 5 output/capture input. tm0 i/o mfp5 timer0event counter input / toggle output usci0 _clk i/o mfp6 usci0 clock pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 5 pa.10 i/o mfp0 general purpose digital i/o pin. i2c1_sda i/o mfp1 i 2 c1 data input/output pin. bpwm0_ch4 i/o mfp4 bpwm0 channel 4 output/capture input. pwm0_brake0 i mfp5 brake input pin 0 of pwm0. usci0 _dat1 i/o mfp6 usci0 dat1 pin. 6 pb.4 i/o mfp0 general purpose digital i/o pin. bpwm0_ch3 i/o mfp4 bpwm0 channel 3 output/capture input. tm2_ext i mfp5 timer2 external counter input usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 7 pb.5 i/o mfp0 general purpose digital i/o pin. bpwm0_ch2 i/o mfp4 bpwm0 channel 2 output/capture input.
nuc121 /125 feb . 23 , 201 7 page 38 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description tm3 i/o mfp5 timer3 event counter input / toggle output usci0 _clk i/o mfp6 usci0 clock pin. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 8 pb.6 i/o mfp0 general purpose digital i/o pin. bpwm0_ch1 i/o mfp4 bpwm0 channel 1 output/capture input. usci0 _dat0 i/o mfp6 usci0 dat0 pin. usci0 _ctl1 i/o mfp7 usci0 ctl1 pin. 9 pb.7 i/o mfp0 general purpose digital i/o pin. bpwm0_ch0 i/o mfp4 bpwm0 channel 0 output/capture input. usci0 _dat1 i/o mfp6 usci0 dat1 pin. usci0 _ctl0 i/o mfp7 usci0 ctl0 pin. 1 0 ldo_cap a mfp0 ldo output pin. 1 1 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 1 2 v ss a mfp0 ground pin for digital circuit. 13 usb_vbus a mfp0 power supply from usb host or hub. 1 4 usb_vdd33_cap a mfp0 internal power regulator output 3.3v decoupling pin. 1 5 usb_d - i mfp0 usb differential signal d - . 16 usb_d+ i mfp0 usb differential signal d+. 17 pc.5 i/o mfp0 general purpose digital i/o pin. uart0_txd o mfp2 data transmitter output pin for uart0. pwm1_ch5 i/o mfp4 pwm1 channel5 output/capture input. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 18 pc.4 i/o mfp0 general purpose digital i/o pin. uart0_rxd i mfp2 data receiver input pin for uart0. spi0_i2smclk o mfp3 i2s0 master clock output pin. pwm1_ch4 i/o mfp4 pwm1 channel4 output/capture input. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 19 pc.3 i/o mfp0 general purpose digital i/o pin. spi0_mosi i/o mfp1 spi0 mosi (master out, slave in) pin. i2c1_sda i/o mfp3 i 2 c1 data input/output pin. pwm1_ch3 i/o mfp4 pwm1 channel3 output/capture input. uart0_ n rts o mfp6 request to send output pin for uart 0 . usci0 _dat0 i/o mfp7 usci0 dat0 pin.
nuc121 /125 feb . 23 , 201 7 page 39 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description 20 pc.2 i/o mfp0 general purpose digital i/o pin. spi0_miso i/o mfp1 spi0 miso (master in, slave out) pin. i2c1_scl i/o mfp3 i 2 c1 clock pin. pwm1_ch2 i/o mfp4 pwm1 channel2 output/capture input. uart0_ n cts i mfp6 clear to send input pin for uart0. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 21 pc.1 i/o mfp0 general purpose digital i/o pin. spi0_clk i/o mfp1 spi0 serial clock pin. pwm1_ch1 i/o mfp4 pwm1 channel1 output/capture input. uart0_txd o mfp6 data transmitter output pin for uart0. usci0 _ctl0 i/o mfp7 usci0 ctl0 pin 22 pc.0 i/o mfp0 general purpose digital i/o pin. spi0_ss i/o mfp1 spi0 slave select pin. pwm1_ch0 i/o mfp4 pwm1 channel0 output/capture input. tm2 i/o mfp5 timer2 event counter input / toggle output uart0_rxd i mfp6 data receiver input pin for uart0. usci0 _clk i/o mfp7 usci0 clock pin. 23 pb.10 i/o mfp0 general purpose digital i/o pin. tm2 i/o mfp1 timer2 event counter input / toggle output spi0_i2smclk o mfp3 i2s0 master clock output pin. pwm0_ch5 i/o mfp4 pwm0 channel5 output/capture input. 24 pb.9 i/o mfp0 general purpose digital i/o pin. tm1 i/o mfp1 timer1 event counter input / toggle output spi0_i2smclk o mfp3 i2s0 master clock output pin. pwm0_ch4 i/o mfp4 pwm0 channel4 output/capture input. 25 pc.13 i/o mfp0 general purpose digital i/o pin. pwm0_ch3 i/o mfp2 pwm0 channel3 output/capture input. clko o mfp3 clock out int0 i mfp5 external interrupt0 input pin. i2c0_sda i/o mfp6 i 2 c0 data input/output pin. 26 pc.12 i/o mfp0 general purpose digital i/o pin. pwm0_ch2 i/o mfp2 pwm0 channel2 output/capture input. spi0_i2smclk o mfp3 i2s0 master clock output pin.
nuc121 /125 feb . 23 , 201 7 page 40 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description clko o mfp4 clock out int0 i mfp5 external interrupt0 input pin. i2c0_scl i/o mfp6 i 2 c0 clock pin. usci0 _ctl1 i/o mfp7 usci0 ctl1 pin. 27 pc.11 i/o mfp0 general purpose digital i/o pin. spi0_mosi i/o mfp3 spi0 mosi (master out, slave in) pin. pwm0_ch1 i/o mfp4 pwm0 channel1 output/capture input. tm1 i/o mfp5 timer1 event counter input / toggle output i2c0_sda i/o mfp6 i 2 c0 data input/output pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 28 pc.10 i/o mfp0 general purpose digital i/o pin. spi0_miso i/o mfp3 spi0 miso (master in, slave out) pin. pwm0_ch0 i/o mfp4 pwm0 channel0 output/capture input. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 2 9 pc.9 i/o mfp0 general purpose digital i/o pin. spi0_clk i/o mfp3 spi0 serial clock pin. pwm0_ch5 i/o mfp4 pwm0 channel5 output/capture input. pwm0_brake1 i mfp5 brake input pin 1 of pwm 0 . usci0 _clk i/o mfp7 usci0 clock pin 3 0 pc.8 i/o mfp0 general purpose digital i/o pin. stadc i mfp2 adc external trigger input. spi0_ss i/o mfp3 spi0 slave select pin. pwm0_ch4 i/o mfp4 pwm0 channel4 output/capture input. pwm1_brake0 i mfp5 brake input pin 0 of pwm 1 . usci0 _ctl0 i/o mfp7 usci0 ctl0 pin 3 1 pa.15 i/o mfp0 general purpose digital i/o pin. pwm0_ch3 i/o mfp1 pwm0 channel3 output/capture input. spi_i2smclk o mfp2 i2s0 master clock output pin. clko o mfp3 clock out pwm1_brake1 i mfp4 brake input pin 1 of pwm1. uart0_ n rts o mfp5 request to send output pin for uart 0 . 32 pa.14 i/o mfp0 general purpose digital i/o pin. pwm0_ch2 i/o mfp1 pwm0 channel2 output/capture input.
nuc121 /125 feb . 23 , 201 7 page 41 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description uart0_ n cts i mfp3 clear to send input pin for uart0. pwm0_brake0 i mfp4 brake input pin 0 of pwm0. 33 pa.13 i/o mfp0 general purpose digital i/o pin. pwm0_ch1 i/o mfp1 pwm0 channel1 output/capture input. i2c1_sda i/o mfp2 i 2 c1 data input/output pin. uart0_txd o mfp3 data transmitter output pin for uart0. 34 pa.12 i/o mfp0 general purpose digital i/o pin. pwm0_ch0 i/o mfp1 pwm0 channel0 output/capture input. i2c1_scl i/o mfp2 i 2 c1 clock pin. uart0_rxd i mfp3 data receiver input pin for uart0. 35 pf.4 i/o mfp0 general purpose digital i/o pin. ice_dat i/o mfp1 serial wired debugger data pin i2c0_sda i/o mfp2 i 2 c0 data input/output pin. uart0_txd o mfp3 data transmitter output pin for uart0. pwm0_ch3 i/o mfp4 pwm0 channel3 output/capture input. 36 pf.5 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin i2c0_scl i/o mfp2 i 2 c0 clock pin. uart0_rxd i mfp3 data receiver input pin for uart0. 37 av dd a mfp0 power supply for internal analog circuit. 38 pd.0 i/o mfp0 general purpose digital i/o pin. adc_ch0 a mfp3 adc channel 0 analog input. uart0_ n rts o mfp5 request to send output pin for uart 0 . usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. spi0_ss i/o mfp7 spi0 slave select pin. 39 pd.1 i/o mfp0 general purpose digital i/o pin. adc_ch1 a mfp3 adc channel 1 analog input. tm0_ext i mfp4 timer0 external counter input uart0_rxd i mfp5 data receiver input pin for uart0. usci0 _clk i/o mfp6 usci0 clock pin. spi0_clk i/o mfp7 spi0 serial clock pin. 40 pd.2 i/o mfp0 general purpose digital i/o pin. adc_ch2 a mfp3 adc channel 2 analog input.
nuc121 /125 feb . 23 , 201 7 page 42 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description tm3 i/o mfp4 timer3 event counter input / toggle output uart0_txd o mfp5 data transmitter output pin for uart0. usci0 _dat1 i/o mfp6 usci0 dat1 pin. spi0_miso i/o mfp7 spi0 miso (master in, slave out) pin. 41 pd.3 i/o mfp0 general purpose digital i/o pin. adc_ch3 a mfp3 adc channel 3 analog input. tm1_ext i mfp4 timer1 external counter input uart0_ n cts i mfp5 clear to send input pin for uart0. usci0 _dat0 i/o mfp6 usci0 dat0 pin. spi0_mosi i/o mfp7 spi0 mosi (master out, slave in) pin. 42 pd.4 i/o mfp0 general purpose digital i/o pin. adc_ch4 a mfp2 adc channel 4 analog input. bpwm1_ch5 i/o mfp4 bpwm1 channel 5 output/capture input. uart0_ n rts o mfp5 request to send output pin for uart 0 . usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. spi0_ss i/o mfp7 spi0 slave select pin. 43 pd.5 i/o mfp0 general purpose digital i/o pin. adc_ch5 a mfp2 adc channel 5 analog input. bpwm1_ch4 i/o mfp4 bpwm1 channel 4 output/capture input. 44 pf.0 i/o mfp0 general purpose digital i/o pin. xt_out o mfp1 external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal output pin. bpwm1_ch3 i/o mfp4 bpwm1 channel 3 output/capture input. tm3 i/o mfp5 timer3 event counter input / toggle output 45 pf.1 i/o mfp0 general purpose digital i/o pin. xt_in i mfp1 external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal input pin. bpwm1_ch2 i/o mfp4 bpwm1 channel 2 output/capture input. tm1_ext i mfp5 timer1 external counter input 46 nreset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 47 pf.2 i/o mfp0 general purpose digital i/o pin. ice_dat i/o mfp1 serial wired debugger data pin i2c0_sda i/o mfp2 i 2 c0 data input/output pin. adc_ch6 a mfp3 adc channel 6 analog input.
nuc121 /125 feb . 23 , 201 7 page 43 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description bpwm1_ch3 i/o mfp4 bpwm1 channel 3 output/capture input. 48 pf.3 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin i2c0_scl i/o mfp2 i 2 c0 clock pin. adc_ch7 a mfp3 adc channel 7 analog input. bpwm1_ch2 i/o mfp4 bpwm1 channel 2 output/capture input. table 4.3 - 2 nuc121 usb series lqfp48 pin description
nuc121 /125 feb . 23 , 201 7 page 44 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.3.3 nuc121 usb series lqfp 64 pin description mfp* = multi - function pin. (re fer to section sys_gpx_mfpl and sys_gpx_mfph) pa.10 mfp5 means sys_gpa_mfph[11:8]=0x5. pc.0 mfp0 means sys_gpc_mfpl[3:0]=0x0. pin no. pin name type mfp * description 1 pb.14 i/o mfp0 general purpose digital i/o pin. int0 i mfp1 external interrupt0 input pin. uart0_ n rts o mfp2 request to send output pin for uart 0. adc_ch9 a mfp3 adc channel 9 analog input. bpwm1_ch0 i/o mfp4 bpwm1 channel 0 output/capture input. spi0_ss i/o mfp7 spi0 slave select pin. 2 pb.13 i/o mfp0 general purpose digital i/o pin. adc_ch10 a mfp3 adc channel 1 0 analog input. usci0 _ctl1 i/o mfp6 usci0 ctl1 pin. 3 pb.12 i/o mfp0 general purpose digital i/o pin. clko o mfp2 clock out adc_ch11 a mfp3 adc channel 1 1 analog input. usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. 4 pa.11 i/o mfp0 general purpose digital i/o pin. i2c1_scl i/o mfp1 i 2 c1 clock pin. bpwm0_ch5 i/o mfp4 bpwm0 channel 5 output/capture input. tm0 i/o mfp5 timer0event counter input / toggle output usci0 _clk i/o mfp6 usci0 clock pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 5 pa.10 i/o mfp0 general purpose digital i/o pin. i2c1_sda i/o mfp1 i 2 c1 data input/output pin. bpwm0_ch4 i/o mfp4 bpwm0 channel 4 output/capture input. pwm0_brake0 i mfp5 brake input pin 0 of pwm0. usci0 _dat1 i/o mfp6 usci0 dat1 pin. 6 pd.8 i/o mfp0 general purpose digital i/o pin. usci0 _dat0 i/o mfp6 usci0 dat0 pin. 7 pd.9 i/o mfp0 general purpose digital i/o pin. pwm0_brake1 i mfp5 brake input pin 1 of pwm 0 . 8 pd.10 i/o mfp0 general purpose digital i/o pin.
nuc121 /125 feb . 23 , 201 7 page 45 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description clko o mfp1 clock out bpwm0_ch5 i/o mfp4 bpwm0 channel 5 output/capture input. 9 pd.11 i/o mfp0 general purpose digital i/o pin. int1 i mfp1 external interrupt1 input pin. bpwm0_ch4 i/o mfp4 bpwm0 channel 4 output/capture input. 10 pb.4 i/o mfp0 general purpose digital i/o pin. bpwm0_ch3 i/o mfp4 bpwm0 channel 3 output/capture input. tm2_ext i mfp5 timer2 external counter input usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 11 pb.5 i/o mfp0 general purpose digital i/o pin. bpwm0_ch2 i/o mfp4 bpwm0 channel 2 output/capture input. tm3 i/o mfp5 timer3 event counter input / toggle output usci0 _clk i/o mfp6 usci0 clock pin. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 12 pb.6 i/o mfp0 general purpose digital i/o pin. bpwm0_ch1 i/o mfp4 bpwm0 channel 1 output/capture input. usci0 _dat0 i/o mfp6 usci0 dat0 pin. usci0 _ctl1 i/o mfp7 usci0 ctl1 pin. 13 pb.7 i/o mfp0 general purpose digital i/o pin. bpwm0_ch0 i/o mfp4 bpwm0 channel 0 output/capture input. usci0 _dat1 i/o mfp6 usci0 dat1 pin. usci0 _ctl0 i/o mfp7 usci0 ctl0 pin. 14 ldo_cap a mfp0 ldo output pin. 15 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 16 v ss a mfp0 ground pin for digital circuit. 17 usb_vbus a mfp0 power supply from usb host or hub. 18 usb_vdd33_cap a mfp0 internal power regulator output 3.3v decoupling pin. 19 usb_d - i mfp0 usb differential signal d - . 20 usb_d+ i mfp0 usb differential signal d+. 21 pb.0 i/o mfp0 general purpose digital i/o pin. uart0_rxd i mfp1 data receiver input pin for uart0. pwm1_ch0 i/o mfp4 pwm1 channel0 output/capture input.
nuc121 /125 feb . 23 , 201 7 page 46 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description 22 pb.1 i/o mfp0 general purpose digital i/o pin. uart0_txd o mfp1 data transmitter output pin for uart0. pwm1_ch1 i/o mfp4 pwm1 channel1 output/capture input. 23 pb.2 i/o mfp0 general purpose digital i/o pin. uart0_ n rts o mfp1 request to send output pin for uart 0 . tm2_ext i mfp2 timer2 external counter input pwm1_ch2 i/o mfp4 pwm1 channel2 output/capture input. 24 pb.3 i/o mfp0 general purpose digital i/o pin. uart0_ n cts i mfp1 clear to send input pin for uart 0 . tm3_ext i mfp2 timer3 external counter input pwm1_ch3 i/o mfp4 pwm1 channel3 output/capture input. 25 pc.5 i/o mfp0 general purpose digital i/o pin. uart0_txd o mfp2 data transmitter output pin for uart0. pwm1_ch5 i/o mfp4 pwm1 channel5 output/capture input. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 26 pc.4 i/o mfp0 general purpose digital i/o pin. uart0_rxd i mfp2 data receiver input pin for uart0. spi0_i2smclk o mfp3 i2s0 master clock output pin. pwm1_ch4 i/o mfp4 pwm1 channel4 output/capture input. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 27 pc.3 i/o mfp0 general purpose digital i/o pin. spi0_mosi i/o mfp1 spi0 mosi (master out, slave in) pin. i2c1_sda i/o mfp3 i 2 c1 data input/output pin. pwm1_ch3 i/o mfp4 pwm1 channel3 output/capture input. uart0_ n rts o mfp6 request to send output pin for uart 0 . usci0 _dat0 i/o mfp7 usci0 dat0 pin. 28 pc.2 i/o mfp0 general purpose digital i/o pin. spi0_miso i/o mfp1 spi0 miso (master in, slave out) pin. i2c1_scl i/o mfp3 i 2 c1 clock pin. pwm1_ch2 i/o mfp4 pwm1 channel2 output/capture input. uart0_ n cts i mfp6 clear to send input pin for uart0. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 29 pc.1 i/o mfp0 general purpose digital i/o pin.
nuc121 /125 feb . 23 , 201 7 page 47 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description spi0_clk i/o mfp1 spi0 serial clock pin. pwm1_ch1 i/o mfp4 pwm1 channel1 output/capture input. uart0_txd o mfp6 data transmitter output pin for uart0. usci0 _ctl0 i/o mfp7 usci0 ctl0 pin 30 pc.0 i/o mfp0 general purpose digital i/o pin. spi0_ss i/o mfp1 spi0 slave select pin. pwm1_ch0 i/o mfp4 pwm1 channel0 output/capture input. tm2 i/o mfp5 timer2 event counter input / toggle output uart0_rxd i mfp6 data receiver input pin for uart0. usci0 _clk i/o mfp7 usci0 clock pin. 31 pb.10 i/o mfp0 general purpose digital i/o pin. tm2 i/o mfp1 timer2 event counter input / toggle output spi0_i2smclk o mfp3 i2s0 master clock output pin. pwm0_ch5 i/o mfp4 pwm0 channel5 output/capture input. 32 pb.9 i/o mfp0 general purpose digital i/o pin. tm1 i/o mfp1 timer1 event counter input / toggle output spi0_i2smclk o mfp3 i2s0 master clock output pin. pwm0_ch4 i/o mfp4 pwm0 channel4 output/capture input. 33 pe.2 i/o mfp0 general purpose digital i/o pin. int1 i mfp1 external interrupt1 input pin. tm0_ext i mfp5 timer0 external counter input i2c0_scl i/o mfp6 i 2 c0 clock pin. usci0 _ctl1 i/o mfp7 usci0 ctl1 pin. 34 pc.13 i/o mfp0 general purpose digital i/o pin. pwm0_ch3 i/o mfp2 pwm0 channel3 output/capture input. clko o mfp3 clock out int0 i mfp5 external interrupt0 input pin. i2c0_sda i/o mfp6 i 2 c0 data input/output pin. 35 pc.12 i/o mfp0 general purpose digital i/o pin. pwm0_ch2 i/o mfp2 pwm0 channel2 output/capture input. spi0_i2smclk o mfp3 i2s0 master clock output pin. clko o mfp4 clock out int0 i mfp5 external interrupt0 input pin.
nuc121 /125 feb . 23 , 201 7 page 48 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description i2c0_scl i/o mfp6 i 2 c0 clock pin. usci0 _ctl1 i/o mfp7 usci0 ctl1 pin. 36 pc.11 i/o mfp0 general purpose digital i/o pin. spi0_mosi i/o mfp3 spi0 mosi (master out, slave in) pin. pwm0_ch1 i/o mfp4 pwm0 channel1 output/capture input. tm1 i/o mfp5 timer1 event counter input / toggle output i2c0_sda i/o mfp6 i 2 c0 data input/output pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 37 pc.10 i/o mfp0 general purpose digital i/o pin. spi0_miso i/o mfp3 spi0 miso (master in, slave out) pin. pwm0_ch0 i/o mfp4 pwm0 channel0 output/capture input. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 38 pe.1 i/o mfp0 general purpose digital i/o pin. stadc i mfp2 adc external trigger input. clko o mfp3 clock out tm3 i/o mfp5 timer3 event counter input / toggle output usci0 _dat1 i/o mfp7 usci0 dat1 pin. 39 pc.9 i/o mfp0 general purpose digital i/o pin. spi0_clk i/o mfp3 spi0 serial clock pin. pwm0_ch5 i/o mfp4 pwm0 channel5 output/capture input. pwm0_brake1 i mfp5 brake input pin 1 of pwm 0 . usci0 _clk i/o mfp7 usci0 clock pin 40 pc.8 i/o mfp0 general purpose digital i/o pin. stadc i mfp2 adc external trigger input. spi0_ss i/o mfp3 spi0 slave select pin. pwm0_ch4 i/o mfp4 pwm0 channel4 output/capture input. pwm1_brake0 i mfp5 brake input pin 0 of pwm 1 . usci0 _ctl0 i/o mfp7 usci0 ctl0 pin 41 pa.15 i/o mfp0 general purpose digital i/o pin. pwm0_ch3 i/o mfp1 pwm0 channel3 output/capture input. spi_i2smclk o mfp2 i2s0 master clock output pin. clko o mfp3 clock out pwm1_brake1 i mfp4 brake input pin 1 of pwm1.
nuc121 /125 feb . 23 , 201 7 page 49 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description uart0_ n rts o mfp5 request to send output pin for uart 0 . 42 pe.0 i/o mfp0 general purpose digital i/o pin. int0 i mfp1 external interrupt0 input pin. clko o mfp3 clock out pwm0_ch3 i/o mfp4 pwm0 channel3 output/capture input. tm1_ext i mfp5 timer1 external counter input usci0 _dat0 i/o mfp7 usci0 dat0 pin. 43 pa.14 i/o mfp0 general purpose digital i/o pin. pwm0_ch2 i/o mfp1 pwm0 channel2 output/capture input. uart0_ n cts i mfp3 clear to send input pin for uart0. pwm0_brake0 i mfp4 brake input pin 0 of pwm0. 44 pa.13 i/o mfp0 general purpose digital i/o pin. pwm0_ch1 i/o mfp1 pwm0 channel1 output/capture input. i2c1_sda i/o mfp2 i 2 c1 data input/output pin. uart0_txd o mfp3 data transmitter output pin for uart0. 45 pa.12 i/o mfp0 general purpose digital i/o pin. pwm0_ch0 i/o mfp1 pwm0 channel0 output/capture input. i2c1_scl i/o mfp2 i 2 c1 clock pin. uart0_rxd i mfp3 data receiver input pin for uart0. 46 pf.4 i/o mfp0 general purpose digital i/o pin. ice_dat i/o mfp1 serial wired debugger data pin i2c0_sda i/o mfp2 i 2 c0 data input/output pin. uart0_txd o mfp3 data transmitter output pin for uart0. pwm0_ch3 i/o mfp4 pwm0 channel3 output/capture input. 47 pf.5 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin i2c0_scl i/o mfp2 i 2 c0 clock pin. uart0_rxd i mfp3 data receiver input pin for uart0. 48 av dd a mfp0 power supply for internal analog circuit. 49 pd.0 i/o mfp0 general purpose digital i/o pin. adc_ch0 a mfp3 adc channel 0 analog input. uart0_ n rts o mfp5 request to send output pin for uart 0 . usci0 _ctl0 i/o mfp6 usci0 ctl0 pin.
nuc121 /125 feb . 23 , 201 7 page 50 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description spi0_ss i/o mfp7 spi0 slave select pin. 50 pd.1 i/o mfp0 general purpose digital i/o pin. adc_ch1 a mfp3 adc channel 1 analog input. tm0_ext i mfp4 timer0 external counter input uart0_rxd i mfp5 data receiver input pin for uart0. usci0 _clk i/o mfp6 usci0 clock pin. spi0_clk i/o mfp7 spi0 serial clock pin. 51 pd.2 i/o mfp0 general purpose digital i/o pin. adc_ch2 a mfp3 adc channel 2 analog input. tm3 i/o mfp4 timer3 event counter input / toggle output uart0_txd o mfp5 data transmitter output pin for uart0. usci0 _dat1 i/o mfp6 usci0 dat1 pin. spi0_miso i/o mfp7 spi0 miso (master in, slave out) pin. 52 pd.3 i/o mfp0 general purpose digital i/o pin. adc_ch3 a mfp3 adc channel 3 analog input. tm1_ext i mfp4 timer1 external counter input uart0_ n cts i mfp5 clear to send input pin for uart0. usci0 _dat0 i/o mfp6 usci0 dat0 pin. spi0_mosi i/o mfp7 spi0 mosi (master out, slave in) pin. 53 pd.4 i/o mfp0 general purpose digital i/o pin. adc_ch4 a mfp2 adc channel 4 analog input. bpwm1_ch5 i/o mfp4 bpwm1 channel 5 output/capture input. uart0_ n rts o mfp5 request to send output pin for uart 0 . usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. spi0_ss i/o mfp7 spi0 slave select pin. 54 pd.5 i/o mfp0 general purpose digital i/o pin. adc_ch5 a mfp2 adc channel 5 analog input. bpwm1_ch4 i/o mfp4 bpwm1 channel 4 output/capture input. 55 pb.15 i/o mfp0 general purpose digital i/o pin. int1 i mfp1 external interrupt1 input pin. tm0_ext i mfp2 timer0 external counter input bpwm1_ch5 i/o mfp4 bpwm1 channel 5 output/capture input. 56 pf.0 i/o mfp0 general purpose digital i/o pin.
nuc121 /125 feb . 23 , 201 7 page 51 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description xt_out o mfp1 external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal output pin. bpwm1_ch3 i/o mfp4 bpwm1 channel 3 output/capture input. tm3 i/o mfp5 timer3 event counter input / toggle output 57 pf.1 i/o mfp0 general purpose digital i/o pin. xt_in i mfp1 external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal input pin. bpwm1_ch2 i/o mfp4 bpwm1 channel 2 output/capture input. tm1_ext i mfp5 timer1 external counter input 58 nreset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 59 v ss a mfp0 ground pin for digital circuit. 60 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 61 pf.2 i/o mfp0 general purpose digital i/o pin. ice_dat i/o mfp1 serial wired debugger data pin i2c0_sda i/o mfp2 i 2 c0 data input/output pin. adc_ch6 a mfp3 adc channel 6 analog input. bpwm1_ch3 i/o mfp4 bpwm1 channel 3 output/capture input. 62 pf.3 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin i2c0_scl i/o mfp2 i 2 c0 clock pin. adc_ch7 a mfp3 adc channel 7 analog input. bpwm1_ch2 i/o mfp4 bpwm1 channel 2 output/capture input. 63 v ss a mfp0 ground pin for digital circuit. 64 pb.8 i/o mfp0 general purpose digital i/o pin. tm0 i/o mfp1 timer0event counter input / toggle output adc_ch8 a mfp3 adc channel 8 analog input. bpwm1_ch1 i/o mfp4 bpwm1 channel 1 output/capture input. table 4.3 - 3 nuc121 usb series lqfp64 pin description
nuc121 /125 feb . 23 , 201 7 page 52 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.3.4 nuc125 usb series qfn33 pin description mfp* = multi - function pin. (ref er to section sys_gpx_mfpl and sys_gpx_mfph) pa.10 mfp5 means sys_gpa_mfph[11:8]=0x5. pc.0 mfp0 means sys_gpc_mfpl[3:0]=0x0. pin no. pin name type mfp * description 1 pb.14 i/o mfp0 general purpose digital i/o pin. int0 i mfp1 external interrupt0 input pin. uart0_ n rts o mfp2 request to send output pin for uart 0. adc_ch9 a mfp3 adc channel 9 analog input. bpwm1_ch0 i/o mfp4 bpwm1 channel 0 output/capture input. spi0_ss i/o mfp7 spi0 slave select pin. 2 pa.11 i/o mfp0 general purpose digital i/o pin. i2c1_scl i/o mfp1 i 2 c1 clock pin. bpwm0_ch5 i/o mfp4 bpwm0 channel 5 output/capture input. tm0 i/o mfp5 timer0event counter input / toggle output usci0 _clk i/o mfp6 usci0 clock pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 3 pa.10 i/o mfp0 general purpose digital i/o pin. i2c1_sda i/o mfp1 i 2 c1 data input/output pin. bpwm0_ch4 i/o mfp4 bpwm0 channel 4 output/capture input. pwm0_brake0 i mfp5 brake input pin 0 of pwm0. usci0 _dat1 i/o mfp6 usci0 dat1 pin. 4 pb.4 i/o mfp0 general purpose digital i/o pin. bpwm0_ch3 i/o mfp4 bpwm0 channel 3 output/capture input. tm2_ext i mfp5 timer2 external counter input usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 5 pb.5 i/o mfp0 general purpose digital i/o pin. bpwm0_ch2 i/o mfp4 bpwm0 channel 2 output/capture input. tm3 i/o mfp5 timer3 event counter input / toggle output usci0 _clk i/o mfp6 usci0 clock pin. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 6 ldo_cap a mfp0 ldo output pin. 7 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function.
nuc121 /125 feb . 23 , 201 7 page 53 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description 8 v ss a mfp0 ground pin for digital circuit. 9 usb_vbus a mfp0 power supply from usb host or hub. 10 usb_vdd33_cap a mfp0 internal power regulator output 3.3v decoupling pin. 11 usb_d - i mfp0 usb differential signal d - . 12 usb_d+ i mfp0 usb differential signal d+. 13 pc.3 i/o mfp0 general purpose digital i/o pin. spi0_mosi i/o mfp1 spi0 mosi (master out, slave in) pin. i2c1_sda i/o mfp3 i 2 c1 data input/output pin. pwm1_ch3 i/o mfp4 pwm1 channel3 output/capture input. uart0_ n rts o mfp6 request to send output pin for uart 0 . usci0 _dat0 i/o mfp7 usci0 dat0 pin. 14 pc.2 i/o mfp0 general purpose digital i/o pin. spi0_miso i/o mfp1 spi0 miso (master in, slave out) pin. i2c1_scl i/o mfp3 i 2 c1 clock pin. pwm1_ch2 i/o mfp4 pwm1 channel2 output/capture input. uart0_ n cts i mfp6 clear to send input pin for uart0. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 15 pc.1 i/o mfp0 general purpose digital i/o pin. spi0_clk i/o mfp1 spi0 serial clock pin. pwm1_ch1 i/o mfp4 pwm1 channel1 output/capture input. uart0_txd o mfp6 data transmitter output pin for uart0. usci0 _ctl0 i/o mfp7 usci0 ctl0 pin 16 pc.0 i/o mfp0 general purpose digital i/o pin. spi0_ss i/o mfp1 spi0 slave select pin. pwm1_ch0 i/o mfp4 pwm1 channel0 output/capture input. tm2 i/o mfp5 timer2 event counter input / toggle output uart0_rxd i mfp6 data receiver input pin for uart0. usci0 _clk i/o mfp7 usci0 clock pin. 17 pc.13 i/o mfp0 general purpose digital i/o pin. pwm0_ch3 i/o mfp2 pwm0 channel3 output/capture input. clko o mfp3 clock out int0 i mfp5 external interrupt0 input pin. i2c0_sda i/o mfp6 i 2 c0 data input/output pin.
nuc121 /125 feb . 23 , 201 7 page 54 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description 18 pc.12 i/o mfp0 general purpose digital i/o pin. pwm0_ch2 i/o mfp2 pwm0 channel2 output/capture input. spi0_i2smclk o mfp3 i2s0 master clock output pin. clko o mfp4 clock out int0 i mfp5 external interrupt0 input pin. i2c0_scl i/o mfp6 i 2 c0 clock pin. usci0 _ctl1 i/o mfp7 usci0 ctl1 pin. 19 pc.11 i/o mfp0 general purpose digital i/o pin. spi0_mosi i/o mfp3 spi0 mosi (master out, slave in) pin. pwm0_ch1 i/o mfp4 pwm0 channel1 output/capture input. tm1 i/o mfp5 timer1 event counter input / toggle output i2c0_sda i/o mfp6 i 2 c0 data input/output pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 20 pc.10 i/o mfp0 general purpose digital i/o pin. spi0_miso i/o mfp3 spi0 miso (master in, slave out) pin. pwm0_ch0 i/o mfp4 pwm0 channel0 output/capture input. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 21 pc.9 i/o mfp0 general purpose digital i/o pin. spi0_clk i/o mfp3 spi0 serial clock pin. pwm0_ch5 i/o mfp4 pwm0 channel5 output/capture input. pwm0_brake1 i mfp5 brake input pin 1 of pwm 0 . usci0 _clk i/o mfp7 usci0 clock pin 22 pc.8 i/o mfp0 general purpose digital i/o pin. stadc i mfp2 adc external trigger input. spi0_ss i/o mfp3 spi0 slave select pin. pwm0_ch4 i/o mfp4 pwm0 channel4 output/capture input. pwm1_brake0 i mfp5 brake input pin 0 of pwm 1 . usci0 _ctl0 i/o mfp7 usci0 ctl0 pin 23 pf.4 i/o mfp0 general purpose digital i/o pin. ice_dat i/o mfp1 serial wired debugger data pin i2c0_sda i/o mfp2 i 2 c0 data input/output pin. uart0_txd o mfp3 data transmitter output pin for uart0. pwm0_ch3 i/o mfp4 pwm0 channel3 output/capture input.
nuc121 /125 feb . 23 , 201 7 page 55 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description 24 pf.5 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin i2c0_scl i/o mfp2 i 2 c0 clock pin. uart0_rxd i mfp3 data receiver input pin for uart0. 25 av dd a mfp0 power supply for internal analog circuit. 26 pd.1 i/o mfp0 general purpose digital i/o pin. adc_ch1 a mfp3 adc channel 1 analog input. tm0_ext i mfp4 timer0 external counter input uart0_rxd i mfp5 data receiver input pin for uart0. usci0 _clk i/o mfp6 usci0 clock pin. spi0_clk i/o mfp7 spi0 serial clock pin. 27 pd.2 i/o mfp0 general purpose digital i/o pin. adc_ch2 a mfp3 adc channel 2 analog input. tm3 i/o mfp4 timer3 event counter input / toggle output uart0_txd o mfp5 data transmitter output pin for uart0. usci0 _dat1 i/o mfp6 usci0 dat1 pin. spi0_miso i/o mfp7 spi0 miso (master in, slave out) pin. 28 pd.3 i/o mfp0 general purpose digital i/o pin. adc_ch3 a mfp3 adc channel 3 analog input. tm1_ext i mfp4 timer1 external counter input uart0_ n cts i mfp5 clear to send input pin for uart0. usci0 _dat0 i/o mfp6 usci0 dat0 pin. spi0_mosi i/o mfp7 spi0 mosi (master out, slave in) pin. 29 pf.0 i/o mfp0 general purpose digital i/o pin. xt_out o mfp1 external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal output pin. bpwm1_ch3 i/o mfp4 bpwm1 channel 3 output/capture input. tm3 i/o mfp5 timer3 event counter input / toggle output 30 pf.1 i/o mfp0 general purpose digital i/o pin. xt_in i mfp1 external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal input pin. bpwm1_ch2 i/o mfp4 bpwm1 channel 2 output/capture input. tm1_ext i mfp5 timer1 external counter input 31 nreset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state.
nuc121 /125 feb . 23 , 201 7 page 56 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description 32 v dd io a mfp0 power supply for pb.14, pa.11, pa.10, pb.4 and pb.5. 33 v ss a mfp0 ground pin for digital circuit. table 4.3 - 4 nuc12 5 usb series qfn33 pin description
nuc121 /125 feb . 23 , 201 7 page 57 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.3.5 nuc12 5 usb series lqfp48 pin description mfp* = multi - function pin. (refer to section sys_gpx_mfpl and sys_gpx_mfph) pa.10 mfp5 means sys_gpa_mfph[11:8]=0x5. pc.0 mfp0 means sys_gpc_mfpl[3:0]=0x0.. pin no. pin name type mfp * description 1 v ss a mfp0 ground pin for digital circuit. 2 v dd io a mfp0 power supply for pb.14, pa.11, pa.10, pb.4, pb.5, pb.6 and pb.7. 3 pb.14 i/o mfp0 general purpose digital i/o pin. int0 i mfp1 external interrupt0 input pin. uart0_ n rts o mfp2 request to send output pin for uart 0. adc_ch9 a mfp3 adc channel 9 analog input. bpwm1_ch0 i/o mfp4 bpwm1 channel 0 output/capture input. spi0_ss i/o mfp7 spi0 slave select pin. 4 pa.11 i/o mfp0 general purpose digital i/o pin. i2c1_scl i/o mfp1 i 2 c1 clock pin. bpwm0_ch5 i/o mfp4 bpwm0 channel 5 output/capture input. tm0 i/o mfp5 timer0event counter input / toggle output usci0 _clk i/o mfp6 usci0 clock pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 5 pa.10 i/o mfp0 general purpose digital i/o pin. i2c1_sda i/o mfp1 i 2 c1 data input/output pin. bpwm0_ch4 i/o mfp4 bpwm0 channel 4 output/capture input. pwm0_brake0 i mfp5 brake input pin 0 of pwm0. usci0 _dat1 i/o mfp6 usci0 dat1 pin. 6 pb.4 i/o mfp0 general purpose digital i/o pin. bpwm0_ch3 i/o mfp4 bpwm0 channel 3 output/capture input. tm2_ext i mfp5 timer2 external counter input usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 7 pb.5 i/o mfp0 general purpose digital i/o pin. bpwm0_ch2 i/o mfp4 bpwm0 channel 2 output/capture input. tm3 i/o mfp5 timer3 event counter input / toggle output usci0 _clk i/o mfp6 usci0 clock pin. usci0 _dat1 i/o mfp7 usci0 dat1 pin.
nuc121 /125 feb . 23 , 201 7 page 58 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description 8 pb.6 i/o mfp0 general purpose digital i/o pin. bpwm0_ch1 i/o mfp4 bpwm0 channel 1 output/capture input. usci0 _dat0 i/o mfp6 usci0 dat0 pin. usci0 _ctl1 i/o mfp7 usci0 ctl1 pin. 9 pb.7 i/o mfp0 general purpose digital i/o pin. bpwm0_ch0 i/o mfp4 bpwm0 channel 0 output/capture input. usci0 _dat1 i/o mfp6 usci0 dat1 pin. usci0 _ctl0 i/o mfp7 usci0 ctl0 pin. 1 0 ldo_cap a mfp0 ldo output pin. 1 1 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 1 2 v ss a mfp0 ground pin for digital circuit. 13 usb_vbus a mfp0 power supply from usb host or hub. 1 4 usb_vdd33_cap a mfp0 internal power regulator output 3.3v decoupling pin. 1 5 usb_d - i mfp0 usb differential signal d - . 16 usb_d+ i mfp0 usb differential signal d+. 17 pc.5 i/o mfp0 general purpose digital i/o pin. uart0_txd o mfp2 data transmitter output pin for uart0. pwm1_ch5 i/o mfp4 pwm1 channel5 output/capture input. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 18 pc.4 i/o mfp0 general purpose digital i/o pin. uart0_rxd i mfp2 data receiver input pin for uart0. spi0_i2smclk o mfp3 i2s0 master clock output pin. pwm1_ch4 i/o mfp4 pwm1 channel4 output/capture input. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 19 pc.3 i/o mfp0 general purpose digital i/o pin. spi0_mosi i/o mfp1 spi0 mosi (master out, slave in) pin. i2c1_sda i/o mfp3 i 2 c1 data input/output pin. pwm1_ch3 i/o mfp4 pwm1 channel3 output/capture input. uart0_ n rts o mfp6 request to send output pin for uart 0 . usci0 _dat0 i/o mfp7 usci0 dat0 pin. 20 pc.2 i/o mfp0 general purpose digital i/o pin. spi0_miso i/o mfp1 spi0 miso (master in, slave out) pin. i2c1_scl i/o mfp3 i 2 c1 clock pin.
nuc121 /125 feb . 23 , 201 7 page 59 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description pwm1_ch2 i/o mfp4 pwm1 channel2 output/capture input. uart0_ n cts i mfp6 clear to send input pin for uart0. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 21 pc.1 i/o mfp0 general purpose digital i/o pin. spi0_clk i/o mfp1 spi0 serial clock pin. pwm1_ch1 i/o mfp4 pwm1 channel1 output/capture input. uart0_txd o mfp6 data transmitter output pin for uart0. usci0 _ctl0 i/o mfp7 usci0 ctl0 pin 22 pc.0 i/o mfp0 general purpose digital i/o pin. spi0_ss i/o mfp1 spi0 slave select pin. pwm1_ch0 i/o mfp4 pwm1 channel0 output/capture input. tm2 i/o mfp5 timer2 event counter input / toggle output uart0_rxd i mfp6 data receiver input pin for uart0. usci0 _clk i/o mfp7 usci0 clock pin. 23 pb.10 i/o mfp0 general purpose digital i/o pin. tm2 i/o mfp1 timer2 event counter input / toggle output spi0_i2smclk o mfp3 i2s0 master clock output pin. pwm0_ch5 i/o mfp4 pwm0 channel5 output/capture input. 24 pb.9 i/o mfp0 general purpose digital i/o pin. tm1 i/o mfp1 timer1 event counter input / toggle output spi0_i2smclk o mfp3 i2s0 master clock output pin. pwm0_ch4 i/o mfp4 pwm0 channel4 output/capture input. 25 pc.13 i/o mfp0 general purpose digital i/o pin. pwm0_ch3 i/o mfp2 pwm0 channel3 output/capture input. clko o mfp3 clock out int0 i mfp5 external interrupt0 input pin. i2c0_sda i/o mfp6 i 2 c0 data input/output pin. 26 pc.12 i/o mfp0 general purpose digital i/o pin. pwm0_ch2 i/o mfp2 pwm0 channel2 output/capture input. spi0_i2smclk o mfp3 i2s0 master clock output pin. clko o mfp4 clock out int0 i mfp5 external interrupt0 input pin. i2c0_scl i/o mfp6 i 2 c0 clock pin.
nuc121 /125 feb . 23 , 201 7 page 60 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description usci0 _ctl1 i/o mfp7 usci0 ctl1 pin. 27 pc.11 i/o mfp0 general purpose digital i/o pin. spi0_mosi i/o mfp3 spi0 mosi (master out, slave in) pin. pwm0_ch1 i/o mfp4 pwm0 channel1 output/capture input. tm1 i/o mfp5 timer1 event counter input / toggle output i2c0_sda i/o mfp6 i 2 c0 data input/output pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 28 pc.10 i/o mfp0 general purpose digital i/o pin. spi0_miso i/o mfp3 spi0 miso (master in, slave out) pin. pwm0_ch0 i/o mfp4 pwm0 channel0 output/capture input. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 2 9 pc.9 i/o mfp0 general purpose digital i/o pin. spi0_clk i/o mfp3 spi0 serial clock pin. pwm0_ch5 i/o mfp4 pwm0 channel5 output/capture input. pwm0_brake1 i mfp5 brake input pin 1 of pwm 0 . usci0 _clk i/o mfp7 usci0 clock pin 3 0 pc.8 i/o mfp0 general purpose digital i/o pin. stadc i mfp2 adc external trigger input. spi0_ss i/o mfp3 spi0 slave select pin. pwm0_ch4 i/o mfp4 pwm0 channel4 output/capture input. pwm1_brake0 i mfp5 brake input pin 0 of pwm 1 . usci0 _ctl0 i/o mfp7 usci0 ctl0 pin 3 1 pa.15 i/o mfp0 general purpose digital i/o pin. pwm0_ch3 i/o mfp1 pwm0 channel3 output/capture input. spi_i2smclk o mfp2 i2s0 master clock output pin. clko o mfp3 clock out pwm1_brake1 i mfp4 brake input pin 1 of pwm1. uart0_ n rts o mfp5 request to send output pin for uart 0 . 32 pa.14 i/o mfp0 general purpose digital i/o pin. pwm0_ch2 i/o mfp1 pwm0 channel2 output/capture input. uart0_ n cts i mfp3 clear to send input pin for uart0. pwm0_brake0 i mfp4 brake input pin 0 of pwm0. 33 pa.13 i/o mfp0 general purpose digital i/o pin.
nuc121 /125 feb . 23 , 201 7 page 61 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description pwm0_ch1 i/o mfp1 pwm0 channel1 output/capture input. i2c1_sda i/o mfp2 i 2 c1 data input/output pin. uart0_txd o mfp3 data transmitter output pin for uart0. 34 pa.12 i/o mfp0 general purpose digital i/o pin. pwm0_ch0 i/o mfp1 pwm0 channel0 output/capture input. i2c1_scl i/o mfp2 i 2 c1 clock pin. uart0_rxd i mfp3 data receiver input pin for uart0. 35 pf.4 i/o mfp0 general purpose digital i/o pin. ice_dat i/o mfp1 serial wired debugger data pin i2c0_sda i/o mfp2 i 2 c0 data input/output pin. uart0_txd o mfp3 data transmitter output pin for uart0. pwm0_ch3 i/o mfp4 pwm0 channel3 output/capture input. 36 pf.5 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin i2c0_scl i/o mfp2 i 2 c0 clock pin. uart0_rxd i mfp3 data receiver input pin for uart0. 37 av dd a mfp0 power supply for internal analog circuit. 38 pd.0 i/o mfp0 general purpose digital i/o pin. adc_ch0 a mfp3 adc channel 0 analog input. uart0_ n rts o mfp5 request to send output pin for uart 0 . usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. spi0_ss i/o mfp7 spi0 slave select pin. 39 pd.1 i/o mfp0 general purpose digital i/o pin. adc_ch1 a mfp3 adc channel 1 analog input. tm0_ext i mfp4 timer0 external counter input uart0_rxd i mfp5 data receiver input pin for uart0. usci0 _clk i/o mfp6 usci0 clock pin. spi0_clk i/o mfp7 spi0 serial clock pin. 40 pd.2 i/o mfp0 general purpose digital i/o pin. adc_ch2 a mfp3 adc channel 2 analog input. tm3 i/o mfp4 timer3 event counter input / toggle output uart0_txd o mfp5 data transmitter output pin for uart0. usci0 _dat1 i/o mfp6 usci0 dat1 pin.
nuc121 /125 feb . 23 , 201 7 page 62 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description spi0_miso i/o mfp7 spi0 miso (master in, slave out) pin. 41 pd.3 i/o mfp0 general purpose digital i/o pin. adc_ch3 a mfp3 adc channel 3 analog input. tm1_ext i mfp4 timer1 external counter input uart0_ n cts i mfp5 clear to send input pin for uart0. usci0 _dat0 i/o mfp6 usci0 dat0 pin. spi0_mosi i/o mfp7 spi0 mosi (master out, slave in) pin. 42 pd.4 i/o mfp0 general purpose digital i/o pin. adc_ch4 a mfp2 adc channel 4 analog input. bpwm1_ch5 i/o mfp4 bpwm1 channel 5 output/capture input. uart0_ n rts o mfp5 request to send output pin for uart 0 . usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. spi0_ss i/o mfp7 spi0 slave select pin. 43 pd.5 i/o mfp0 general purpose digital i/o pin. adc_ch5 a mfp2 adc channel 5 analog input. bpwm1_ch4 i/o mfp4 bpwm1 channel 4 output/capture input. 44 pf.0 i/o mfp0 general purpose digital i/o pin. xt_out o mfp1 external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal output pin. bpwm1_ch3 i/o mfp4 bpwm1 channel 3 output/capture input. tm3 i/o mfp5 timer3 event counter input / toggle output 45 pf.1 i/o mfp0 general purpose digital i/o pin. xt_in i mfp1 external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal input pin. bpwm1_ch2 i/o mfp4 bpwm1 channel 2 output/capture input. tm1_ext i mfp5 timer1 external counter input 46 nreset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 47 pf.2 i/o mfp0 general purpose digital i/o pin. ice_dat i/o mfp1 serial wired debugger data pin i2c0_sda i/o mfp2 i 2 c0 data input/output pin. adc_ch6 a mfp3 adc channel 6 analog input. bpwm1_ch3 i/o mfp4 bpwm1 channel 3 output/capture input. 48 pf.3 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin
nuc121 /125 feb . 23 , 201 7 page 63 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description i2c0_scl i/o mfp2 i 2 c0 clock pin. adc_ch7 a mfp3 adc channel 7 analog input. bpwm1_ch2 i/o mfp4 bpwm1 channel 2 output/capture input. table 4.3 - 5 nuc12 5 usb series lqfp48 pin description
nuc121 /125 feb . 23 , 201 7 page 64 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.3.6 nuc12 5 usb series lqfp 64 pin description mfp* = multi - function pin. (refer to section sys_gpx_mfpl and sys_gpx_mfph) pa.10 mfp5 means sys_gpa_mfph[11:8]=0x5. pc.0 mfp0 means sys_gpc_mfpl[3:0]=0x0. pin no. pin name type mfp * description 1 pb.14 i/o mfp0 general purpose digital i/o pin. int0 i mfp1 external interrupt0 input pin. uart0_ n rts o mfp2 request to send output pin for uart 0. adc_ch9 a mfp3 adc channel 9 analog input. bpwm1_ch0 i/o mfp4 bpwm1 channel 0 output/capture input. spi0_ss i/o mfp7 spi0 slave select pin. 2 pb.13 i/o mfp0 general purpose digital i/o pin. adc_ch10 a mfp3 adc channel 1 0 analog input. usci0 _ctl1 i/o mfp6 usci0 ctl1 pin. 3 pb.12 i/o mfp0 general purpose digital i/o pin. clko o mfp2 clock out adc_ch11 a mfp3 adc channel 1 1 analog input. usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. 4 pa.11 i/o mfp0 general purpose digital i/o pin. i2c1_scl i/o mfp1 i 2 c1 clock pin. bpwm0_ch5 i/o mfp4 bpwm0 channel 5 output/capture input. tm0 i/o mfp5 timer0event counter input / toggle output usci0 _clk i/o mfp6 usci0 clock pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 5 pa.10 i/o mfp0 general purpose digital i/o pin. i2c1_sda i/o mfp1 i 2 c1 data input/output pin. bpwm0_ch4 i/o mfp4 bpwm0 channel 4 output/capture input. pwm0_brake0 i mfp5 brake input pin 0 of pwm0. usci0 _dat1 i/o mfp6 usci0 dat1 pin. 6 pd.8 i/o mfp0 general purpose digital i/o pin. usci0 _dat0 i/o mfp6 usci0 dat0 pin. 7 pd.9 i/o mfp0 general purpose digital i/o pin. pwm0_brake1 i mfp5 brake input pin 1 of pwm 0 . 8 pd.10 i/o mfp0 general purpose digital i/o pin.
nuc121 /125 feb . 23 , 201 7 page 65 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description clko o mfp1 clock out bpwm0_ch5 i/o mfp4 bpwm0 channel 5 output/capture input. 9 pd.11 i/o mfp0 general purpose digital i/o pin. int1 i mfp1 external interrupt1 input pin. bpwm0_ch4 i/o mfp4 bpwm0 channel 4 output/capture input. 10 pb.4 i/o mfp0 general purpose digital i/o pin. bpwm0_ch3 i/o mfp4 bpwm0 channel 3 output/capture input. tm2_ext i mfp5 timer2 external counter input usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 11 pb.5 i/o mfp0 general purpose digital i/o pin. bpwm0_ch2 i/o mfp4 bpwm0 channel 2 output/capture input. tm3 i/o mfp5 timer3 event counter input / toggle output usci0 _clk i/o mfp6 usci0 clock pin. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 12 pb.6 i/o mfp0 general purpose digital i/o pin. bpwm0_ch1 i/o mfp4 bpwm0 channel 1 output/capture input. usci0 _dat0 i/o mfp6 usci0 dat0 pin. usci0 _ctl1 i/o mfp7 usci0 ctl1 pin. 13 pb.7 i/o mfp0 general purpose digital i/o pin. bpwm0_ch0 i/o mfp4 bpwm0 channel 0 output/capture input. usci0 _dat1 i/o mfp6 usci0 dat1 pin. usci0 _ctl0 i/o mfp7 usci0 ctl0 pin. 14 ldo_cap a mfp0 ldo output pin. 15 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 16 v ss a mfp0 ground pin for digital circuit. 17 usb_vbus a mfp0 power supply from usb host or hub. 18 usb_vdd33_cap a mfp0 internal power regulator output 3.3v decoupling pin. 19 usb_d - i mfp0 usb differential signal d - . 20 usb_d+ i mfp0 usb differential signal d+. 21 pb.0 i/o mfp0 general purpose digital i/o pin. uart0_rxd i mfp1 data receiver input pin for uart0. pwm1_ch0 i/o mfp4 pwm1 channel0 output/capture input.
nuc121 /125 feb . 23 , 201 7 page 66 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description 22 pb.1 i/o mfp0 general purpose digital i/o pin. uart0_txd o mfp1 data transmitter output pin for uart0. pwm1_ch1 i/o mfp4 pwm1 channel1 output/capture input. 23 pb.2 i/o mfp0 general purpose digital i/o pin. uart0_ n rts o mfp1 request to send output pin for uart 0 . tm2_ext i mfp2 timer2 external counter input pwm1_ch2 i/o mfp4 pwm1 channel2 output/capture input. 24 pb.3 i/o mfp0 general purpose digital i/o pin. uart0_ n cts i mfp1 clear to send input pin for uart 0 . tm3_ext i mfp2 timer3 external counter input pwm1_ch3 i/o mfp4 pwm1 channel3 output/capture input. 25 pc.5 i/o mfp0 general purpose digital i/o pin. uart0_txd o mfp2 data transmitter output pin for uart0. pwm1_ch5 i/o mfp4 pwm1 channel5 output/capture input. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 26 pc.4 i/o mfp0 general purpose digital i/o pin. uart0_rxd i mfp2 data receiver input pin for uart0. spi0_i2smclk o mfp3 i2s0 master clock output pin. pwm1_ch4 i/o mfp4 pwm1 channel4 output/capture input. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 27 pc.3 i/o mfp0 general purpose digital i/o pin. spi0_mosi i/o mfp1 spi0 mosi (master out, slave in) pin. i2c1_sda i/o mfp3 i 2 c1 data input/output pin. pwm1_ch3 i/o mfp4 pwm1 channel3 output/capture input. uart0_ n rts o mfp6 request to send output pin for uart 0 . usci0 _dat0 i/o mfp7 usci0 dat0 pin. 28 pc.2 i/o mfp0 general purpose digital i/o pin. spi0_miso i/o mfp1 spi0 miso (master in, slave out) pin. i2c1_scl i/o mfp3 i 2 c1 clock pin. pwm1_ch2 i/o mfp4 pwm1 channel2 output/capture input. uart0_ n cts i mfp6 clear to send input pin for uart0. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 29 pc.1 i/o mfp0 general purpose digital i/o pin.
nuc121 /125 feb . 23 , 201 7 page 67 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description spi0_clk i/o mfp1 spi0 serial clock pin. pwm1_ch1 i/o mfp4 pwm1 channel1 output/capture input. uart0_txd o mfp6 data transmitter output pin for uart0. usci0 _ctl0 i/o mfp7 usci0 ctl0 pin 30 pc.0 i/o mfp0 general purpose digital i/o pin. spi0_ss i/o mfp1 spi0 slave select pin. pwm1_ch0 i/o mfp4 pwm1 channel0 output/capture input. tm2 i/o mfp5 timer2 event counter input / toggle output uart0_rxd i mfp6 data receiver input pin for uart0. usci0 _clk i/o mfp7 usci0 clock pin. 31 pb.10 i/o mfp0 general purpose digital i/o pin. tm2 i/o mfp1 timer2 event counter input / toggle output spi0_i2smclk o mfp3 i2s0 master clock output pin. pwm0_ch5 i/o mfp4 pwm0 channel5 output/capture input. 32 pb.9 i/o mfp0 general purpose digital i/o pin. tm1 i/o mfp1 timer1 event counter input / toggle output spi0_i2smclk o mfp3 i2s0 master clock output pin. pwm0_ch4 i/o mfp4 pwm0 channel4 output/capture input. 33 pe.2 i/o mfp0 general purpose digital i/o pin. int1 i mfp1 external interrupt1 input pin. tm0_ext i mfp5 timer0 external counter input i2c0_scl i/o mfp6 i 2 c0 clock pin. usci0 _ctl1 i/o mfp7 usci0 ctl1 pin. 34 pc.13 i/o mfp0 general purpose digital i/o pin. pwm0_ch3 i/o mfp2 pwm0 channel3 output/capture input. clko o mfp3 clock out int0 i mfp5 external interrupt0 input pin. i2c0_sda i/o mfp6 i 2 c0 data input/output pin. 35 pc.12 i/o mfp0 general purpose digital i/o pin. pwm0_ch2 i/o mfp2 pwm0 channel2 output/capture input. spi0_i2smclk o mfp3 i2s0 master clock output pin. clko o mfp4 clock out int0 i mfp5 external interrupt0 input pin.
nuc121 /125 feb . 23 , 201 7 page 68 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description i2c0_scl i/o mfp6 i 2 c0 clock pin. usci0 _ctl1 i/o mfp7 usci0 ctl1 pin. 36 pc.11 i/o mfp0 general purpose digital i/o pin. spi0_mosi i/o mfp3 spi0 mosi (master out, slave in) pin. pwm0_ch1 i/o mfp4 pwm0 channel1 output/capture input. tm1 i/o mfp5 timer1 event counter input / toggle output i2c0_sda i/o mfp6 i 2 c0 data input/output pin. usci0 _dat0 i/o mfp7 usci0 dat0 pin. 37 pc.10 i/o mfp0 general purpose digital i/o pin. spi0_miso i/o mfp3 spi0 miso (master in, slave out) pin. pwm0_ch0 i/o mfp4 pwm0 channel0 output/capture input. usci0 _dat1 i/o mfp7 usci0 dat1 pin. 38 pe.1 i/o mfp0 general purpose digital i/o pin. stadc i mfp2 adc external trigger input. clko o mfp3 clock out tm3 i/o mfp5 timer3 event counter input / toggle output usci0 _dat1 i/o mfp7 usci0 dat1 pin. 39 pc.9 i/o mfp0 general purpose digital i/o pin. spi0_clk i/o mfp3 spi0 serial clock pin. pwm0_ch5 i/o mfp4 pwm0 channel5 output/capture input. pwm0_brake1 i mfp5 brake input pin 1 of pwm 0 . usci0 _clk i/o mfp7 usci0 clock pin 40 pc.8 i/o mfp0 general purpose digital i/o pin. stadc i mfp2 adc external trigger input. spi0_ss i/o mfp3 spi0 slave select pin. pwm0_ch4 i/o mfp4 pwm0 channel4 output/capture input. pwm1_brake0 i mfp5 brake input pin 0 of pwm 1 . usci0 _ctl0 i/o mfp7 usci0 ctl0 pin 41 pa.15 i/o mfp0 general purpose digital i/o pin. pwm0_ch3 i/o mfp1 pwm0 channel3 output/capture input. spi_i2smclk o mfp2 i2s0 master clock output pin. clko o mfp3 clock out pwm1_brake1 i mfp4 brake input pin 1 of pwm1.
nuc121 /125 feb . 23 , 201 7 page 69 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description uart0_ n rts o mfp5 request to send output pin for uart 0 . 42 pe.0 i/o mfp0 general purpose digital i/o pin. int0 i mfp1 external interrupt0 input pin. clko o mfp3 clock out pwm0_ch3 i/o mfp4 pwm0 channel3 output/capture input. tm1_ext i mfp5 timer1 external counter input usci0 _dat0 i/o mfp7 usci0 dat0 pin. 43 pa.14 i/o mfp0 general purpose digital i/o pin. pwm0_ch2 i/o mfp1 pwm0 channel2 output/capture input. uart0_ n cts i mfp3 clear to send input pin for uart0. pwm0_brake0 i mfp4 brake input pin 0 of pwm0. 44 pa.13 i/o mfp0 general purpose digital i/o pin. pwm0_ch1 i/o mfp1 pwm0 channel1 output/capture input. i2c1_sda i/o mfp2 i 2 c1 data input/output pin. uart0_txd o mfp3 data transmitter output pin for uart0. 45 pa.12 i/o mfp0 general purpose digital i/o pin. pwm0_ch0 i/o mfp1 pwm0 channel0 output/capture input. i2c1_scl i/o mfp2 i 2 c1 clock pin. uart0_rxd i mfp3 data receiver input pin for uart0. 46 pf.4 i/o mfp0 general purpose digital i/o pin. ice_dat i/o mfp1 serial wired debugger data pin i2c0_sda i/o mfp2 i 2 c0 data input/output pin. uart0_txd o mfp3 data transmitter output pin for uart0. pwm0_ch3 i/o mfp4 pwm0 channel3 output/capture input. 47 pf.5 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin i2c0_scl i/o mfp2 i 2 c0 clock pin. uart0_rxd i mfp3 data receiver input pin for uart0. 48 av dd a mfp0 power supply for internal analog circuit. 49 pd.0 i/o mfp0 general purpose digital i/o pin. adc_ch0 a mfp3 adc channel 0 analog input. uart0_ n rts o mfp5 request to send output pin for uart 0 . usci0 _ctl0 i/o mfp6 usci0 ctl0 pin.
nuc121 /125 feb . 23 , 201 7 page 70 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description spi0_ss i/o mfp7 spi0 slave select pin. 50 pd.1 i/o mfp0 general purpose digital i/o pin. adc_ch1 a mfp3 adc channel 1 analog input. tm0_ext i mfp4 timer0 external counter input uart0_rxd i mfp5 data receiver input pin for uart0. usci0 _clk i/o mfp6 usci0 clock pin. spi0_clk i/o mfp7 spi0 serial clock pin. 51 pd.2 i/o mfp0 general purpose digital i/o pin. adc_ch2 a mfp3 adc channel 2 analog input. tm3 i/o mfp4 timer3 event counter input / toggle output uart0_txd o mfp5 data transmitter output pin for uart0. usci0 _dat1 i/o mfp6 usci0 dat1 pin. spi0_miso i/o mfp7 spi0 miso (master in, slave out) pin. 52 pd.3 i/o mfp0 general purpose digital i/o pin. adc_ch3 a mfp3 adc channel 3 analog input. tm1_ext i mfp4 timer1 external counter input uart0_ n cts i mfp5 clear to send input pin for uart0. usci0 _dat0 i/o mfp6 usci0 dat0 pin. spi0_mosi i/o mfp7 spi0 mosi (master out, slave in) pin. 53 pd.4 i/o mfp0 general purpose digital i/o pin. adc_ch4 a mfp2 adc channel 4 analog input. bpwm1_ch5 i/o mfp4 bpwm1 channel 5 output/capture input. uart0_ n rts o mfp5 request to send output pin for uart 0 . usci0 _ctl0 i/o mfp6 usci0 ctl0 pin. spi0_ss i/o mfp7 spi0 slave select pin. 54 pd.5 i/o mfp0 general purpose digital i/o pin. adc_ch5 a mfp2 adc channel 5 analog input. bpwm1_ch4 i/o mfp4 bpwm1 channel 4 output/capture input. 55 pb.15 i/o mfp0 general purpose digital i/o pin. int1 i mfp1 external interrupt1 input pin. tm0_ext i mfp2 timer0 external counter input bpwm1_ch5 i/o mfp4 bpwm1 channel 5 output/capture input. 56 pf.0 i/o mfp0 general purpose digital i/o pin.
nuc121 /125 feb . 23 , 201 7 page 71 of 150 rev 1 .0 0 nuc121 /125 series datasheet pin no. pin name type mfp * description xt_out o mfp1 external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal output pin. bpwm1_ch3 i/o mfp4 bpwm1 channel 3 output/capture input. tm3 i/o mfp5 timer3 event counter input / toggle output 57 pf.1 i/o mfp0 general purpose digital i/o pin. xt_in i mfp1 external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal input pin. bpwm1_ch2 i/o mfp4 bpwm1 channel 2 output/capture input. tm1_ext i mfp5 timer1 external counter input 58 nreset i mfp0 external reset input: active low, with an internal pull - up. set this pin low reset to initial state. 59 v ss a mfp0 ground pin for digital circuit. 60 v dd a mfp0 power supply for i/o ports and ldo source for internal pll and digital function. 61 pf.2 i/o mfp0 general purpose digital i/o pin. ice_dat i/o mfp1 serial wired debugger data pin i2c0_sda i/o mfp2 i 2 c0 data input/output pin. adc_ch6 a mfp3 adc channel 6 analog input. bpwm1_ch3 i/o mfp4 bpwm1 channel 3 output/capture input. 62 pf.3 i/o mfp0 general purpose digital i/o pin. ice_clk i mfp1 serial wired debugger clock pin i2c0_scl i/o mfp2 i 2 c0 clock pin. adc_ch7 a mfp3 adc channel 7 analog input. bpwm1_ch2 i/o mfp4 bpwm1 channel 2 output/capture input. 63 v ss a mfp0 ground pin for digital circuit. 64 v dd io a mfp0 power supply for pb.14, pb.13, pb.12, pa.11, pa.10, pd.8, pd.9, pd.10, pd.11, pb.4, pb.5, pb.6 and pb.7. table 4.3 - 6 nuc12 5 usb series lqfp64 pin description
nuc121 /125 feb . 23 , 201 7 page 72 of 150 rev 1 .0 0 nuc121 /125 series datasheet 4.3.7 gpio multi - function pin summary mfp* = multi - function pin. (ref er to section sys_gpx_mfpl and sys_gpx_mfph) pa.10 mfp5 means sys_gpa_mfph[11:8]=0x5. pc.0 mfp0 means sys_gpc_mfpl[3:0]=0x0. group pin name gpio mfp * type description adc0 adc0_ch0 pd.0 mfp3 a adc0 analog input. adc0_ch1 pd.1 mfp3 a adc1 analog input. adc0_ch2 p d .2 mfp 3 a adc2 analog input. adc0_ch3 p d .3 mfp 3 a adc3 analog input. adc0_ch4 p d .4 mfp 2 a adc4 analog input. adc0_ch5 p d . 5 mfp 2 a adc5 analog input. adc0_ch6 pf.2 mfp3 a adc6 analog input. adc0_ch7 pf.3 mfp3 a adc7 analog input. adc0_ch8 pb.8 mfp3 a adc8 analog input. adc0_ch9 pb.14 mfp3 a adc9 analog input. adc0_ch10 pb.13 mfp3 a adc10 analog input. adc0_ch11 pb.12 mfp3 a adc11 analog input. stadc pc.8 mfp2 i adc external trigger input. stadc pe.1 mfp2 i adc external trigger input b pwm0 bpwm0_ch0 pb.7 mfp4 i/o bpwm0 output/capture input. bpwm0_ch1 pb.6 mfp4 i/o bpwm0 output/capture input. bpwm0_ch2 pb.5 mfp4 i/o bpwm0 output/capture input. bpwm0_ch3 pb.4 mfp4 i/o bpwm0 output/capture input. bpwm0_ch4 pa.10 mfp4 i/o bpwm0 output/capture input. bpwm0_ch4 pd.11 mfp4 i/o bpwm0 output/capture input. bpwm0_ch5 pa.11 mfp4 i/o bpwm0 output/capture input. bpwm0_ch5 pd.10 mfp4 i/o bpwm0 output/capture input. bpwm1 bpwm1_ch0 pb.14 mfp4 i/o bpwm1 output/capture input. bpwm1_ch1 pb.8 mfp4 i/o bpwm1 output/capture input. bpwm1_ch2 pf.1 mfp4 i/o bpwm1 output/capture input. bpwm1_ch2 pf.3 mfp4 i/o bpwm1 output/capture input. bpwm1_ch3 pf.0 mfp4 i/o bpwm1 output/capture input. bpwm1_ch3 pf.2 mfp4 i/o bpwm1 output/capture input. bpwm1_ch4 pd.5 mfp4 i/o bpwm1 output/capture input.
nuc121 /125 feb . 23 , 201 7 page 73 of 150 rev 1 .0 0 nuc121 /125 series datasheet group pin name gpio mfp * type description bpwm1_ch5 pb.15 mfp4 i/o bpwm1 output/capture input. bpwm1_ch5 pd.4 mfp4 i/o bpwm1 output/capture input. clko clko pa.15 mfp3 o clock out. clko pb.12 mfp2 o clock out . clko pc.12 mfp4 o clock out. clko pc.13 mfp3 o clock out. clko pd.10 mfp1 o clock out . clko pe.0 mfp3 o clock out . clko pe.1 mfp3 o clock out. i2c0 i2c0_scl pc.12 mfp6 i/o i2c0 clock pin. i2c0_scl pe.2 mfp6 i/o i2c0 clock pin. i2c0_scl pf.3 mfp2 i/o i2c0 clock pin. i2c0_scl pf.5 mfp2 i/o i2c0 clock pin. i2c0_sda pc.11 mfp6 i/o i2c0 data input/output pin. i2c0_sda pc.13 mfp6 i/o i2c0 data input/output pin. i2c0_sda pf.2 mfp2 i/o i2c0 data input/output pin. i2c0_sda pf.4 mfp2 i/o i2c0 data input/output pin. i2c1 i2c1_scl pa.11 mfp1 i/o i2c1 clock pin. i2c1_scl pa.12 mfp2 i/o i2c1 clock pin. i2c1_scl pc.2 mfp3 i/o i2c1 clock pin. i2c1_sda pa.10 mfp1 i/o i2c1 data input/output pin. i2c1_sda pa.13 mfp2 i/o i2c1 data input/output pin. i2c1_sda pc.3 mfp3 i/o i2c1 data input/output pin. ice ice_clk p f . 5 mfp1 i serial wired debugger clock pin . ice_dat p f . 4 mfp1 i/o serial wired debugger data pin . int0 int0 pb.14 mfp1 i external interrupt0 input pin. int0 pc.12 mfp5 i external interrupt0 input pin. int0 pc.13 mfp5 i external interrupt0 input pin. int0 pe.0 mfp1 i external interrupt0 input pin. int1 int1 pb.15 mfp1 i external interrupt1 input pin. int1 pd.11 mfp1 i external interrupt1 input pin. int1 pe.2 mfp1 i external interrupt1 input pin. pwm0 pwm0_brake0 pa.10 mfp5 i pwm0 brak e input 0 .
nuc121 /125 feb . 23 , 201 7 page 74 of 150 rev 1 .0 0 nuc121 /125 series datasheet group pin name gpio mfp * type description pwm0_brake0 pa.14 mfp4 i pwm0 brak e input 0 . pwm0_brake1 pc.9 mfp5 i pwm0 brak e input 1 . pwm0_brake1 pd.9 mfp5 i pwm0 brak e input 1 . pwm0_ch0 pa.12 mfp1 i/o pwm0 output/capture input. pwm0_ch0 pc.10 mfp4 i/o pwm0 output/capture input. pwm0_ch1 pa.13 mfp1 i/o pwm0 output/capture input. pwm0_ch1 pc.11 mfp4 i/o pwm0 output/capture input. pwm0_ch2 pa.14 mfp1 i/o pwm0 output/capture input. pwm0_ch2 pc.12 mfp2 i/o pwm0 output/capture input. pwm0_ch3 pa.15 mfp1 i/o pwm0 output/capture input. pwm0_ch3 pc.13 mfp2 i/o pwm0 output/capture input. pwm0_ch3 pe.0 mfp4 i/o pwm0 output/capture input. pwm0_ch3 pf.4 mfp4 i/o pwm0 output/capture input. pwm0_ch4 pb.9 mfp4 i/o pwm0 output/capture input. pwm0_ch4 pc.8 mfp4 i/o pwm0 output/capture input. pwm0_ch5 pb.10 mfp4 i/o pwm0 output/capture input. pwm0_ch5 pc.9 mfp4 i/o pwm0 output/capture input. pwm1 pwm1_brake0 pc.8 mfp4 i pwm1 brak e input 0 . pwm1_brake1 pa.15 mfp4 i pwm1 brak e input 1 . pwm1_ch0 pb.0 mfp4 i/o pwm1 output/capture input. pwm1_ch0 pc.0 mfp4 i/o pwm1 output/capture input. pwm1_ch1 pb.1 mfp4 i/o pwm1 output/capture input. pwm1_ch1 pc.1 mfp4 i/o pwm1 output/capture input. pwm1_ch2 pb.2 mfp4 i/o pwm1 output/capture input. pwm1_ch2 pc.2 mfp4 i/o pwm1 output/capture input. pwm1_ch3 pb.3 mfp4 i/o pwm1 output/capture input. pwm1_ch3 pc.3 mfp4 i/o pwm1 output/capture input. pwm1_ch4 pc.4 mfp4 i/o pwm1 output/capture input. pwm1_ch5 pc.5 mfp4 i/o pwm1 output/capture input. spi0 spi0_clk pc.1 mfp1 i/o spi0 serial clock pin. spi0_clk pc.9 mfp3 i/o spi0 serial clock pin. spi0_clk pd.1 mfp7 i/o spi0 serial clock pin. spi0_miso0 pc.2 mfp1 i/o spi0 1st miso (master in, slave out) pin.
nuc121 /125 feb . 23 , 201 7 page 75 of 150 rev 1 .0 0 nuc121 /125 series datasheet group pin name gpio mfp * type description spi0_miso0 pc.10 mfp3 i/o spi0 1st miso (master in, slave out) pin. spi0_miso0 pd.2 mfp7 i/o spi0 1st miso (master in, slave out) pin. spi0_mosi0 pc.3 mfp1 i/o spi0 1st mosi (master out, slave in) pin. spi0_mosi0 pc.11 mfp3 i/o spi0 1st mosi (master out, slave in) pin. spi0_mosi0 pd.3 mfp7 i/o spi0 1st mosi (master out, slave in) pin. spi0_ss pb.14 mfp7 i/o spi0 slave select pin. spi0_ss pc.0 mfp1 i/o spi0 slave select pin. spi0_ss pc.8 mfp3 i/o spi0 slave select pin. spi0_ss pd.0 mfp7 i/o spi0 slave select pin. spi0_ss pd.4 mfp7 i/o spi0 slave select pin. spi0_ i2smclk pa.15 mfp2 o i2s0 master clock output pin. spi0_ i2smclk pb.9 mfp3 o i2s0 master clock output pin. spi0_ i2smclk pb.10 mfp3 o i2s0 master clock output pin. spi0_ i2smclk pc.4 mfp3 o i2s0 master clock output pin. spi0_ i2smclk pc.12 mfp3 o i2s0 master clock output pin. tm0 tm0 pa.11 mfp5 i/o timer0 event counter input / toggle output . tm0 pb.8 mfp1 i/o timer0 event counter input / toggle output . tm0_ext pb.15 mfp 2 i timer0 external counter input . tm0_ext pd.1 mfp 4 i timer0 external counter input . tm0_ext pe.2 mfp5 i timer0 external counter input . tm1 tm1 pb.9 mfp5 i/o timer1 event counter input / toggle output . tm1 p c.11 mfp1 i/o timer1 event counter input / toggle output . tm1_ext pd.3 mfp4 i timer1 external counter input . tm1_ext pf.1 mfp5 i timer1 external counter input . tm1_ext pe.3 mfp5 i timer1 external counter input. tm2 tm2 pb.10 mfp1 i/o timer2 event counter input / toggle output . tm2 pc.0 mfp5 i/o timer2 event counter input / toggle output . tm2_ext pb.2 mfp2 i timer2 external counter input . tm2_ext pb.4 mfp5 i timer2 external counter input . tm3 tm3 pb.5 mfp5 i/o timer3 event counter input / toggle output . tm3 pd.2 mfp4 i/o timer3 event counter input / toggle output . tm3 pe.1 mfp5 i/o timer3 event counter input / toggle output . tm3 pf.0 mfp5 i/o timer3 event counter input / toggle output .
nuc121 /125 feb . 23 , 201 7 page 76 of 150 rev 1 .0 0 nuc121 /125 series datasheet group pin name gpio mfp * type description tm3_ext pb.3 mfp2 i timer3 external counter input . uart0 uart0_rxd pa12 mfp3 i data receiver input pin for uart0. uart0_rxd pb.0 mfp1 i data receiver input pin for uart0. uart0_rxd pc.0 mfp6 i data receiver input pin for uart0. uart0_rxd pc.4 mfp2 i data receiver input pin for uart0. uart0_rxd pd.1 mfp5 i data receiver input pin for uart0. uart0_rxd pf.5 mfp3 i data receiver input pin for uart0. uart0_txd pa.13 mfp3 o data transmitter output pin for uart0. uart0_txd pb.1 mfp1 o data transmitter output pin for uart0. uart0_txd pc.1 mfp6 o data transmitter output pin for uart0. uart0_txd pc.5 mfp2 o data transmitter output pin for uart0. uart0_txd pd.2 mfp5 o data transmitter output pin for uart0. uart0_txd pf.4 mfp3 o data transmitter output pin for uart0. uart0_ncts pa.14 mfp3 i clear to send input pin for uart0. uart0_ncts pb.3 mfp1 i clear to send input pin for uart0. uart0_ncts pc.2 mfp6 i clear to send input pin for uart0. uart0_ncts pd.3 mfp5 i clear to send input pin for uart0. uart0_nrts pa.15 mfp5 o request to send output pin for uart0. uart0_nrts pb.2 mfp1 o request to send output pin for uart0. uart0_nrts pb.14 mfp2 o request to send output pin for uart0. uart0_nrts pc.3 mfp6 o request to send output pin for uart0. uart0_nrts pd.0 mfp5 o request to send output pin for uart0. uart0_nrts pd.4 mfp5 o request to send output pin for uart0. usci0 usci0_clk pc.0 mfp7 i/o usci0 clock pin. usci0_clk pc.9 mfp7 i/o usci0 clock pin. usci0_clk pd.1 mfp6 i/o usci0 clock pin. usci0_ctl0 pb.4 mfp6 i/o usci0 ctl0 pin. usci0_ctl0 pb.7 mfp7 i/o usci0 ctl0 pin. usci0_ctl0 pb.12 mfp6 i/o usci0 ctl0 pin. usci0_ctl0 pc.1 mfp7 i/o usci0 ctl0 pin. usci0_ctl0 pc.8 mfp7 i/o usci0 ctl0 pin. usci0_ctl0 pd.0 mfp6 i/o usci0 ctl0 pin. usci0_ctl0 pd.4 mfp6 i/o usci0 ctl0 pin.
nuc121 /125 feb . 23 , 201 7 page 77 of 150 rev 1 .0 0 nuc121 /125 series datasheet group pin name gpio mfp * type description usci0_ctl1 pb6 mfp7 i/o usci0 ctl1 pin. usci0_ctl1 pb.13 mfp6 i/o usci0 ctl1 pin. usci0_ctl1 pc.12 mfp7 i/o usci0 ctl1 pin. usci0_ctl1 pe.2 mfp7 i/o usci0 ctl1 pin. usci0_dat0 pa.11 mfp7 i/o usci0 dat0 pin. usci0_dat0 pb4 mfp7 i/o usci0 dat0 pin. usci0_dat0 pb.6 mfp6 i/o usci0 dat0 pin. usci0_dat0 pc.3 mfp7 i/o usci0 dat0 pin. usci0_dat0 pc.5 mfp7 i/o usci0 dat0 pin. usci0_dat0 pc.11 mfp7 i/o usci0 dat0 pin. usci0_dat0 pd.3 mfp6 i/o usci0 dat0 pin. usci0_dat0 pd.8 mfp6 i/o usci0 dat0 pin. usci0_dat0 pe.0 mfp7 i/o usci0 dat0 pin. usci0_dat1 pa.10 mfp6 i/o usci0 dat1 pin. usci0_dat1 pb.5 mfp7 i/o usci0 dat1 pin. usci0_dat1 pb.7 mfp6 i/o usci0 dat1 pin. usci0_dat1 pc.2 mfp7 i/o usci0 dat1 pin. usci0_dat1 pc.4 mfp7 i/o usci0 dat1 pin. usci0_dat1 pc.10 mfp7 i/o usci0 dat1 pin. usci0_dat1 pd.2 mfp6 i/o usci0 dat1 pin. usci0_dat1 pe.1 mfp7 i/o usci0 dat1 pin. x t x t _in pf.1 mfp1 i external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal in put pin. x t _out pf.0 mfp1 o external 4~24 mhz (high speed) or 32.768 khz (low speed) crystal output pin. table 4.3 - 7 nuc121 /125 gpio multi - function table
nuc121 /125 feb . 23 , 201 7 page 78 of 150 rev 1 .0 0 nuc121 /125 series datasheet 5 block diagram numicro ? nuc121 /125 block diagram 5.1 figure 5.1 - 1 numicro ? nuc121 /125 block diagram
nuc121 /125 feb . 23 , 201 7 page 79 of 150 rev 1 .0 0 nuc121 /125 series datasheet 6 functional descripti on arm ? cortex ? - m0 core 6.1 the cortex ? - m 0 processor, a configurable, multistage, 32 - bit risc processor, has three amba ahb - lite interfaces for best parallel performance and includes an nvic component. the processor with optional hardware debug functionality can execute thumb code and is compatibl e with other cortex - m profile processors. the profile supports two modes - thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only be issued in handler mode. thread mode is entered on reset, and can be entered as a result of an exception return. the cortex ? - m 0 is a processor with the same capability as the cortex ? - m 0 processor and includes floating point arithmetic functionality. the numicro ? nuc121 /125 series is embedded with cortex ? - m 0 processor. thro ughout this document, the name cortex ? - m 0 refers to both cortex ? - m 0 and cortex ? - m 0 processors. figure 6.1 - 1 shows the functional controller of the processor. figure 6.1 - 1 cortex ? - m0 block diagram the implemented device provides: ? a low gate count processor: ? armv6 - m thumb ? instruction set ? thumb - 2 technology ? armv6 - m compliant 24 - bit systick timer ? a 32 - bit hardware multiplier ? system interface supported with little - endian data accesses ? ability to have deterministic, fixed - latency, interrupt handling ? load/store - multiples and multicycle - multiplies that can be abandoned an d restarted to facilitate rapid interrupt handling c o r t e x - m 0 p r o c e s s o r c o r e n e s t e d v e c t o r e d i n t e r r u p t c o n t r o l l e r ( n v i c ) b r e a k p o i n t a n d w a t c h p o i n t u n i t d e b u g g e r i n t e r f a c e b u s m a t r i x d e b u g a c c e s s p o r t ( d a p ) d e b u g c o r t e x - m 0 p r o c e s s o r c o r t e x - m 0 c o m p o n e n t s w a k e u p i n t e r r u p t c o n t r o l l e r ( w i c ) i n t e r r u p t s s e r i a l w i r e o r j t a g d e b u g p o r t a h b - l i t e i n t e r f a c e
nuc121 /125 feb . 23 , 201 7 page 80 of 150 rev 1 .0 0 nuc121 /125 series datasheet ? c application binary interface compliant exception model. this is the armv6 - m, c application binary interface (c - abi) compliant exception model that enables the use of pure c functions as interrupt handler s ? low power sleep mode entry using the wait for interrupt (wfi), wait for event (wfe) instructions, or return from interrupt sleep - on - exit feature ? nvic : ? 32 external interrupt inputs, each with four levels of priority ? dedicated non - maskable interrupt (nmi) input ? supports for both level - sensitive and pulse - sensitive interrupt lines ? supports wake - up interrupt controller (wic) and, providing ultra - low power sleep mode ? debug support: ? four hardware breakpoints ? two watchpoints ? program counter sampling register (pcsr) for non - intrusive code profiling ? single step and vector catch capabilities ? bus interfaces: ? single 32 - bit amba - 3 ahb - lite system interface that provides simple integration to all system peripherals and memory ? single 32 - bit slave port that supports the dap (debug access port)
nuc121 /125 feb . 23 , 201 7 page 81 of 150 rev 1 .0 0 nuc121 /125 series datasheet system manager 6.2 6.2.1 overview the system manager provides the functions of system control, power modes, wake - up sources, reset sources , system memory map , product id and multi - function pin control . the following sections describe th e functions for ? system reset ? power modes and wake - up sources ? system power distributio n ? sram memory orginizatio n ? system control r egister for part number id, c hip r eset and m ulti - function p in c ontrol ? system timer (systick) ? nested vectored interrupt controller (nvic) ? system control register 6.2.2 system reset the system reset can be issued by one of the events listed below . the se reset event flags can be read from sys_rststs register to determine the reset source . hardware reset can reset chip through perip heral reset signals. software reset can trigger reset through control registers. ? hardware reset sources C power - on reset (por) C low level on the nreset pin C watchdog time - out reset and window watchdog reset (wdt/wwdt reset) C low voltage reset (lvr) C brown - out d etector reset (bod reset) C cpu lockup reset ? software reset sources C chip reset will reset whole chip by writing 1 to chiprst (sys_iprst0[0]) C mcu reset to reboot but keeping the booting setting from aprom or ldrom by writing 1 to sysresetreq (aircr[2]) C cpu reset for cortex? - m 0 core only by writing 1 to cpurst (sys_iprst0[1 ])
nuc121 /125 feb . 23 , 201 7 page 82 of 150 rev 1 .0 0 nuc121 /125 series datasheet figure 6.2 - 1 system reset sources l o w v o l t a g e r e s e t p o w e r - o n r e s e t b r o w n - o u t r e s e t r e s e t p u l s e w i d t h 3 . 2 m s w d t / w w d t r e s e t s y s t e m r e s e t ~ 5 0 k o h m @ 5 v r e s e t p u l s e w i d t h 2 s y s t e m c l o c k s n r e s e t v d d a v d d c h i p r e s e t c h i p r s t ( s y s _ i p r s t 0 [ 0 ] ) c p u r e s e t c p u r s t ( s y s _ i p r s t 0 [ 1 ] ) c p u l o c k u p r e s e t m c u r e s e t s y s r s t r e q ( a i r c r [ 2 ] ) l v r e n ( s y s _ b o d c t l [ 7 ] ) b o d r s t e n ( s y s _ b o d c t l [ 3 ] ) p o r o f f ( s y s _ p o r c t l [ 1 5 : 0 ] ) r e s e t p u l s e w i d t h 6 4 w d t c l o c k s r e s e t p u l s e w i d t h 2 s y s t e m c l o c k s g l i t c h f i l t e r 3 2 u s s o f t w a r e r e s e t r e s e t c o n t r o l l e r
nuc121 /125 feb . 23 , 201 7 page 83 of 150 rev 1 .0 0 nuc121 /125 series datasheet there are a total of 9 reset sources in the numicro ? family. in general, cpu reset is used to reset cortex - m 0 only; the other reset sources will reset cortex - m 0 and all peripherals. however, there are small differences between each reset source and they are listed in table 6.2 - 1 . reset sources register por n reset wdt lvr bod lockup chip mcu cpu sys_rststs 0x001 bit 1 = 1 bit 2 = 1 bit 3 = 1 bit 4 = 1 bit 8 = 1 bit 0 = 1 bit 5 = 1 bit 7 = 1 chiprst (sys_iprst0[0]) 0x0 - - - - - - - - boden (sys_bodctl[0]) reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 reload from config0 reload from config0 - bodvl (sys_bodctl[2:1]) bodrsten (sys_bodctl[3]) hxten (clk_pwrctl[0]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 lxten (clk_pwrctl[1]) 0x0 - - - - - - - - wdtcken (clk_apbclk0[0]) 0x1 - 0x1 - - - 0x1 - - hclksel (clk_clksel0[2:0]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - wdtsel (clk_clksel1[1:0]) 0x3 0x3 - - - - - - - hxtstb (clk_status[0]) 0x0 - - - - - - - - lxtstb (clk_status[1]) 0x0 - - - - - - - - pllstb (clk_status[2]) 0x0 - - - - - - - - hircstb (clk_status[4]) 0x0 - - - - - - - - clksfail (clk_status[7]) 0x0 0x0 - - - - - - - rsten (wdt_ctl[1]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 - - wdten (wdt_ctl[7]) wdt_ctl 0x0700 0x0700 0x0700 0x0700 0x0700 - 0x0700 - -
nuc121 /125 feb . 23 , 201 7 page 84 of 150 rev 1 .0 0 nuc121 /125 series datasheet except bit 1 and bit 7. wdt_altctl 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - wwdt_rldcnt 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - wwdt_ctl 0x3f0800 0x3f0800 0x3f0800 0x3f0800 0x3f0800 - 0x3f0800 - - wwdt_status 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - wwdt_cnt 0x3f 0x3f 0x3f 0x3f 0x3f - 0x3f - - bs (fmc_ispctl[1]) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 - - bl (fmc_ispctl[16]) fmc_dfba reload from config1 reload from config1 reload from config1 reload from config1 reload from config1 - reload from config1 - - cbs (fmc_ispsts[2:1)) reload from config0 reload from config0 reload from config0 reload from config0 reload from config0 - reload from config0 - - vecmap (fmc_ispsts[23:9]) reload base on config0 reload base on config0 reload base on config0 reload base on config0 reload base on config0 - reload base on config0 - - other peripheral registers reset value - fmc registers reset value note: - means that the value of register keeps original setting. table 6.2 - 1 reset value of registers nreset reset 6.2.2.1 the nreset reset means to generate a reset signal by pulling low nreset pin, which is an asynchronous reset input pin and can be used to reset system at any time. when the nreset voltage is lower than 0.2 v dd and the state keeps longer than 3 2 us (glitch filter), chip will be reset. the nreset reset will control the chip in reset state until the nreset voltage rises above 0.7 v dd and the state keeps longer than 3 2 us (glitch filter). the pinrf(sys_rststs[1]) will be set to 1 if the previous reset source is nreset reset. figure 6.2 - 2 shows the nreset reset waveform.
nuc121 /125 feb . 23 , 201 7 page 85 of 150 rev 1 .0 0 nuc121 /125 series datasheet figure 6.2 - 2 nreset reset waveform power - on reset (por) 6.2.2.2 the power - on reset (por) is used to generate a stable system reset signal and forces the system to be reset when power - on to avoid unexpected behavior of mcu. when applying the power to mcu, the por module will detect the rising voltage and generate reset signal to system until the voltage is ready for mcu operation. at por reset, the porf(sys_rststs[0]) will be set to 1 to indicate there is a por reset event. the porf(sys_rststs[0]) bit can be cleared by writing 1 to it. figure 6.2 - 3 shows the power - on reset waveform. figure 6.2 - 3 power - on reset (por) waveform low voltage reset (lvr) 6.2.2.3 if the low voltage reset function is enabled by setting the low voltage reset enable bit lvren (sys_bodctl[7]) to 1, after 200us delay, lvr detection circuit will be stable and the lvr function will be active. then lvr function will detect av dd during system operation. when the av dd voltage is lower than v lvr and the state keeps longer than de - glitch time set by lvrdgsel (sys_bodctl[14:12]), chip will be reset. the lvr reset will control the chip in reset state until the av dd voltage rises above v lvr and the state keeps longer than de - glitch time set by lvrdgsel (sys_bodctl[14:12]). the lv rf(sys_rststs[3]) will be set to 1 if the previous reset source is lvr reset. the default setting of low voltage reset is enabled without de - glitch function. figure 6.2 - 4 shows the low voltage reset waveform. n r e s e t 0 . 2 v d d 0 . 7 v d d n r e s e t r e s e t 3 2 u s 3 2 u s v d d v p o r p o w e r - o n r e s e t 0 . 1 v
nuc121 /125 feb . 23 , 201 7 page 86 of 150 rev 1 .0 0 nuc121 /125 series datasheet figure 6.2 - 4 low voltage reset (lvr) waveform brown - out detector reset (bod reset) 6.2.2.4 if the brown - out detector (bod) function is enabled by setting the brown - out detector enable bit boden (sys_bodctl[0]), brown - out detector function will detect av dd during system operation. when the av dd voltage is lower than v bod which is decided by bod_en (bodcr[0]) and bod_vl (bodcr[2:1]) and the state keeps longer than de - glitch time set by boddgsel (sys_bodctl[10:8]) , chip will be reset. the bod reset will contr ol the chip in reset state until the av dd voltage rises above v bod and the state keeps longer than de - glitch time set by boddgsel (sys_bodctl[10:8]) . the default value of boden, bodvl and bodrsten (sys_bodctl[3]) is set by flash controller user configuratio n register cboden (config0 [23]), cbov (config0 [22:21]) and cborst(config0[20]) respectively. user can determine the initial bod setting by setting the config0 register. figure 6. 2 - 5 shows the brown - out detector waveform. a v d d v l v r l o w v o l t a g e r e s e t t 1 ( < l v r d g s e l ) t 2 ( = l v r d g s e l ) t 3 ( = l v r d g s e l ) l v r e n 2 0 0 u s d e l a y f o r l v r s t a b l e
nuc121 /125 feb . 23 , 201 7 page 87 of 150 rev 1 .0 0 nuc121 /125 series datasheet figure 6. 2 - 5 brown - out detector (bod) waveform watchdog timer reset (wdt) 6.2.2.5 in most industrial applications, system reliability is very important. to automatically recover the mcu from failure status is one way to improve system reliability. the watchdog timer(wdt) is widely used to check if the system works fine. if the mcu is cr ashed or out of control, it may cause the watchdog time - out. user may decide to enable system reset during watchdog time - out to recover the system and take action for the system crash/out - of - control after reset. software can check if the reset is caused b y watchdog time - out to indicate the previous reset is a watchdog reset and handle the failure of mcu after watchdog time - out reset by checking wdtrf(sys_rststs[2]). cpu lockup reset 6.2.2.6 cpu enters lockup status after cpu produces hardfault at hardfault handler and chip gives immediate indication of seriously errant kernel software. this is the result of the cpu being locked because of an unrecoverable exception following the activation of the processors built in system state protection hardware. when ch ip enters debug mode, the cpu lockup reset will be ignored. cpu reset, chip reset and mcu reset 6.2.2.7 the cpu reset means only cortex ? - m0 core is reset and all other peripherals remain the same status after cpu reset. user can set the cpurst(sys_iprst0[1]) to 1 to assert the cpu reset a v d d v b o d l b o d o u t b o d r s t e n b r o w n - o u t r e s e t t 1 ( < b o d d g s e l ) t 2 ( = b o d d g s e l ) t 3 ( = b o d d g s e l ) h y s t e r e s i s v b o d h
nuc121 /125 feb . 23 , 201 7 page 88 of 150 rev 1 .0 0 nuc121 /125 series datasheet signal. the chip reset is same with power - on reset. the cpu and all peripherals are reset and bs(fmc_ispctl[1]) bit is automatically reloaded from config0 setting. user can set the chiprst(sys_iprst0[1]) to 1 to assert the chip res et signal. the mcu reset is similar with chip reset. the difference is that bs(fmc_ispctl[1]) will not be reloaded from config0 setting and keep its original software setting for booting from aprom or ldrom. user can set the sysresetreq(aircr[2]) to 1 to a ssert the mcu reset. 6.2.3 power modes and wake - up sources there are several wake - up sources in idle mode and power - down mode. table 6.2 - 2 lists the available clocks for each power mode. power mode normal mode idle mode power - down mode definition cpu is in active state cpu is in sleep state cpu is in sleep state and all clocks stop except lxt and lirc. sram content retended. entry condition c hip is in normal mode after system reset released cpu executes wfi instruction. cpu sets sleep mode enable and power down enable and executes wfi instruction. wake - up sources n/a all interrupts wdt, i2c, tim er, uart, bod, gpio, eint, usci and usbd . available clocks all all except cpu clock lxt and lirc after wake - up n/a cpu back to normal mode cpu back to normal mode table 6.2 - 2 power mode difference table figure 6.2 - 6 power mode state machine n o r m a l m o d e c p u c l o c k o n h x t , h i r c , l x t , l i r c , h c l k , p c l k o n f l a s h o n p o w e r - d o w n m o d e c p u c l o c k o f f h x t , h i r c , h c l k , p c l k o f f f l a s h h a l t s y s t e m r e s e t r e l e a s e d c p u e x e c u t e s w f i i n t e r r u p t s o c c u r i d l e m o d e c p u c l o c k o f f h x t , h i r c , l x t , l i r c , h c l k , p c l k o n f l a s h h a l t 1 . s c r ( s c b [ 2 ] ) = 1 2 . p d _ e n ( p w r c t l [ 7 ] ) = 1 a n d p d w t c p u ( p w r c t l [ 8 ] ) = 1 3 . c p u e x e c u t e s w f i w a k e - u p e v e n t s o c c u r l x t , l i r c o n
nuc121 /125 feb . 23 , 201 7 page 89 of 150 rev 1 .0 0 nuc121 /125 series datasheet 1. lxt (32768 hz xtl) on or off depends on sw setting in run mode. 2. lirc (10 khz osc) on or off depends on s/w setting in run mode. 3. if timer clock source is selected as lirc/lxt and lirc/lxt is on. 4. if wdt clock source is selected as lirc and lirc is on. 5. if uart clock source is selected as lxt and lxt is on. normal mode idle mode power - down mode hxt (4~2 4 mhz xtl) on on halt hirc ( 48 mhz osc) on on halt lxt (32 768 hz xtl) on on on/off 1 lirc (10 khz osc) on on on/off 2 pll on on halt ldo on on on cpu on halt halt hclk/pclk on on halt sram retention on on on flash on on halt gpio on on halt p dma on on halt t i m e r on on on/off 3 b pwm on on halt pwm on on halt wdt on on on/off 4 wwdt on on halt usci on on halt uart on on on/off 5 i 2 c on on halt spi /i 2 s on on halt usb d on on halt adc on on halt table 6.2 - 3 clocks in power modes wake - up s ources in power - down m ode: wdt, i2c, timer, uart, bod, gpio , eint , usci and usbd after chip enters power down, the following wake - up sources can wake chip up to normal mode. table 6.2 - 4 lists the condition about how to enter power - down mode again for each peripheral.
nuc121 /125 feb . 23 , 201 7 page 90 of 150 rev 1 .0 0 nuc121 /125 series datasheet *user needs to wait this condition before setting pd_en(pwrctl[6]) and execute wfi to enter power - down mode. wake - up source wake - up condition system can enter power - down mode again condition * bod brown - out detector interrupt after software writes 1 to clear sys_bodctl[bodif]. gpio gpio interrupt after software write 1 to clear the intsrc [n] bit. timer timer interrupt after software writes 1 to clear twkf ( timer x _intsts [1]) and t i f ( timer x _intsts [0]) . wdt wdt interrupt after software writes 1 to clear wkf ( wdt_ctl [5]) (write protect). uart rx data wake - up a fter software writes 1 to clear datwkif ( uart x _intsts [17]). ncts wake - up a fter software writes 1 to clear ctswkif ( uart x _intsts [16]) . i 2 c f alling edge in the i2c_sda or i2c_clk after software writes 1 to clear wkif ( i2c_wksts[0]). usci usb d remote wake - up after software writes 1 to clear busif ( usbd_intsts [0]). table 6.2 - 4 condition of entering power - down mode again 6.2.4 system power distribution in this chip, power distribution is divided into four segments: ? analog power from av dd and av ss provides the power for analog components operation. ? digital power from v dd and v ss supplies the power to the internal regulator which provides a fixed 1.8 v power for digital operation and i/o pins. ? usb transceiver power from vbus offers the pow er for operating the usb transceiver. ? a dedicated power from v ddio supplies the power for pa.10, pa.11, pb. 4 ~ pb. 7 , pb.1 2 ~ pb. 1 4 and pd.8 ~ 11 of nuc125. the outputs of internal voltage regulators, ldo and vdd33, require an external capacitor which should be located close to the corresponding pin. analog power (av dd ) should be the same voltage level of the digital power (v dd ). figure 6.2 - 7 shows the power distrib ution of the numicro ? nuc121 and nuc125 .
nuc121 /125 feb . 23 , 201 7 page 91 of 150 rev 1 .0 0 nuc121 /125 series datasheet figure 6.2 - 7 numicro ? nuc121 / 125 power distribution diagram u s b t r a n s c e i v e r a v d d a v s s v d d v s s u s b _ v b u s u s b _ d + u s b _ d - 4 8 m h z i r c o s c i l l a t o r 1 0 k h z i r c o s c i l l a t o r s r a m p l l 5 v 3 . 3 v l d o i o c e l l 5 v 1 . 8 v l d o p o r 5 0 p o r 1 8 b r o w n - o u t d e t e c t o r l o w v o l t a g e r e s e t t e m p e r a t u r e s e n s o r h x t / l x t d i g i t a l l o g i c f l a s h 1 2 - b i t a d c i n t e r n a l r e f e r e n c e v o l t a g e p o w e r o n c o n t r o l x t 1 _ o u t x t 1 _ i n g p i o e x c e p t p a . 1 0 , p a . 1 1 , p b . 4 ~ p b . 7 , p b . 1 2 ~ p b . 1 4 a n d p d . 8 ~ 1 1 o f n u c 1 2 5 1 . 8 v 3 . 3 v 5 . 0 v u s b _ v d d 3 3 _ c a p l d o _ c a p 1 u f 1 u f n u c 1 2 1 / 1 2 5 p o w e r d i s t r i b u t i o n i o c e l l p a . 1 0 , p a . 1 1 , p b . 4 ~ p b . 7 , p b . 1 2 ~ p b . 1 4 a n d p d . 8 ~ 1 1 o f n u c 1 2 5 v d d i o
nuc121 /125 feb . 23 , 201 7 page 92 of 150 rev 1 .0 0 nuc121 /125 series datasheet clock controller 6.3 6.3.1 overview the clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. the clock controller also implements the power control function with the individually clock on/off control, clock source selection and a clock divider. the chip will not enter power - down mo de until cpu sets the power - down enable bit pden(clk_pwrctl[7]) and cortex ? - m 0 core executes the wfi instruction. after that, chip enters power - down mode and wait for wake - up interrupt source triggered to leave power - down mode. in power - down mode, the clock controller turns off the 4~24 mhz external high speed crystal (hxt) and 48 m hz internal high speed rc oscillator (hirc) to reduce the overall system power consumption. figure 6.3 - 1 show s the clock generator and the overview of the clock source control.
nuc121 /125 feb . 23 , 201 7 page 93 of 150 rev 1 .0 0 nuc121 /125 series datasheet figure 6.3 - 1 clock generator global view diagram 1 0 c l k _ p l l c t l [ 1 9 ] 4 8 m h z ( h i r c ) 4 ~ 2 4 m h z ( h x t ) p l l f o u t 1 1 1 0 1 1 0 1 0 0 0 1 h x t l x t h x t h c l k h i r c / 2 0 0 0 1 / 2 1 / 2 1 / 2 c l k _ c l k s e l 0 [ 5 : 3 ] 1 0 s y s t i c k t m r 3 u a r t p d m a i 2 c 1 f m c w d t p w m 0 b p w m 0 t m r 0 t m r 1 t m r 2 c p u 3 2 . 7 6 8 k h z ( l x t ) 1 0 k h z ( l i r c ) 1 1 1 0 1 0 0 0 1 0 0 0 p c l k l x t h x t 0 1 1 0 1 0 0 0 1 p l l f o u t l x t h x t l i r c 0 0 0 c l k _ c l k s e l 0 [ 2 : 0 ] s y s t _ c t r l [ 2 ] c p u c l k 1 / ( h c l k d i v + 1 ) p c l k 1 c p u c l k h c l k h i r c / 2 c l k _ c l k s e l 1 [ 1 0 : 8 ] c l k _ c l k s e l 1 [ 1 4 : 1 2 ] c l k _ c l k s e l 1 [ 1 8 : 1 6 ] c l k _ c l k s e l 1 [ 2 2 : 2 0 ] 1 0 p l l f o u t p c l k 0 c l k _ c l k s e l 1 [ 2 8 ] c l k _ c l k s e l 1 [ 3 0 ] h i r c / 2 l i r c 1 1 1 0 c l k _ c l k s e l 1 [ 1 : 0 ] h c l k 1 / 2 0 4 8 1 / ( u a r t d i v + 1 ) h i r c / 2 h x t 0 1 l x t 1 1 0 1 0 0 p l l f o u t h x t l x t c l k _ c l k s e l 1 [ 2 5 : 2 4 ] 1 1 1 h i r c / 2 1 0 1 l i r c 0 1 1 t 0 ~ t 3 1 / ( u s b d i v + 1 ) p l l f o u t p c l k 0 h x t h i r c p l l f o u t c l k _ c l k s e l 2 [ 2 5 : 2 4 ] 1 1 1 0 0 1 0 0 a d c p c l k 0 h x t h i r c / 2 p l l f o u t c l k _ c l k s e l 1 [ 3 : 2 ] 1 1 1 0 0 1 0 0 b o d l i r c 1 / ( a d c d i v + 1 ) w w d t l x t 1 1 1 0 c l k _ c l k s e l 1 [ 3 1 : 3 0 ] p c l k 0 1 / 2 0 4 8 s p i 1 0 0 h i r c 1 0 1 p l l _ f o u t / 2 u s c i p c l k 0 u s b 1 0 h i r c c l k _ c l k s e l 3 [ 8 ] i 2 c 0 g p i o p w m 1 b p w m 1 1 0 p l l f o u t p c l k 1 c l k _ c l k s e l 1 [ 2 9 ] c l k _ c l k s e l 1 [ 3 1 ] h i r c / 2 1 0 h c l k h x t h i r c / 2 l x t c l k _ c l k s e l 2 [ 4 : 2 ] 0 1 1 0 1 0 0 0 1 0 0 0 c l o c k o u t p u t h i r c u s b _ s o f _ d e t 1 1 1 1 0 1
nuc121 /125 feb . 23 , 201 7 page 94 of 150 rev 1 .0 0 nuc121 /125 series datasheet 6.3.2 clock generator the clock generator consists of 5 clock sources, which are listed below: ? 32.768 khz external low - speed crystal oscillator ( l xt) ? 4~24 mhz external high speed crystal oscillator (hxt) ? programmable pll output clock frequency ( pllfout ), pll source can be selected from external 4~24 mhz external high speed crystal (hxt) or 24 mhz (i nternal high speed oscillator , hirc /2 ) ? 4 8 mhz internal high speed rc oscillator (hirc) ? 10 khz internal low speed rc oscillator (lirc) each of these clock sources has certain stable time to wait for clock operating at stable frequency. when clock source is enabled, a stable counter start counting and correlated clock stable index (hircstb(clk_status[4]), lircstb(clk_status[3]), pllstb(clk_status[2]), hxtstb(clk_status[0]) and lxtstb(clk_status[1]) are set to 1 after stable counter value reach a define value as shown in the following table. system and peripheral can use the clock as its operating clock only when correlate c lock stable index is set to 1. the clock stable index will auto clear when user disables the clock source (lircen(clk_pwr ctl[3]), hircen( clk_pwrctl[2]),xtlen(clk_pwrctl[1:0]) and pd(clk_pllctl[16]). besides, the clock stable index of hxt, hirc and pll will auto clear when chip enter power - down and clock stable counter will re - counting after chip wake - up if correlate clock is enabled. clock source clock stable count v alue clock stable t ime hxt 4096 hxt clock s 341.33 us for 12 mhz pll i ts based on the value of stbsel (clk_pllctl[23]) stbsel = 0, stable count is 6144 pll clocks. stbsel = 1, stable count is 12288 pll clocks. (default) stbsel = 0 122.88 us for 50 mhz stbsel = 1 : 245.76 us for 50 mhz hirc 512 hirc clocks 10.667 us for 48mhz lirc 1 lirc clock 100 us for 10 khz l xt 8192 lxt clock 250 ms for 32 khz table 6.3 - 1 clock stable count value table
nuc121 /125 feb . 23 , 201 7 page 95 of 150 rev 1 .0 0 nuc121 /125 series datasheet figure 6.3 - 2 clock generator block diagram p f . 0 e x t e r n a l 4 ~ 2 4 m h z c r y s t a l ( h x t ) x t l e n ( c l k _ p w r c t l [ 1 : 0 ] ) = 0 1 p f . 1 i n t e r n a l 4 8 m h z o s c i l l a t o r ( h i r c ) h i r c e n ( c l k _ p w r c t l [ 2 ] ) 0 1 p l l p l l s r c ( c l k _ p l l c t l [ 1 9 ] ) p l l f o u t e x t e r n a l 3 2 . 7 6 8 k h z c r y s t a l ( l x t ) l x t x t l e n ( c l k _ p w r c t l [ 1 : 0 ] ) = 1 0 i n t e r n a l 1 0 k h z o s c i l l a t o r ( l i r c ) l i r c e n ( c l k _ p w r c t l [ 3 ] ) h x t h i r c l i r c
nuc121 /125 feb . 23 , 201 7 page 96 of 150 rev 1 .0 0 nuc121 /125 series datasheet 6.3.3 system clock and systick clock the system clock has 5 clock sources, which were generated from clock generator block. the clock source switch depends on the register hclksel (clk_clksel0 [2:0]). the block diagram is shown in figure 6.3 - 3 figure 6.3 - 3 system clock block diagram there are two clock fail detectors to observe hxt and lxt clock source if stop and they have individual enable and interrupt control. when hxt fail detector is enabled, the hirc clock is enabled automatically. when lxt detector is enabled, the lirc clock is enabled automatically. when hxt clock fail detector is enabled, the system cl ock will auto switch to hirc /2 (24 mhz) if hxt clock stop being detected on the following condition: system clock source comes from hxt or system clock source comes from pll with hxt as the input of pll. if hxt clock stop condition is detected, the hxtfif (clk_clkdsts[0]) is set to 1 and chip will enter interrupt if hxtfie (clk_clkdctl[5]) is set to 1. user can trying to recover hxt by disable hxt and enable hxt again to check if the clock stable bit is set to 1 or not. if hxt clock stable bit is set to 1, it means hxt is recover to oscillate after re - enable action and user can switch system clock to hxt again. the hxt clock stop detect and system clock switch to hirc /2 (24 mhz) procedure is shown in figure 6.3 - 4 h c l k s e l ( c l k _ c l k s e l 0 [ 2 : 0 ] ) 1 / ( h c l k _ n + 1 ) h c l k d i v ( c l k _ c l k d i v 0 [ 3 : 0 ] ) c p u i n p o w e r d o w n m o d e c p u a h b a p b 1 c p u c l k h c l k p c l k 1 1 / ( h c l k _ n + 1 ) 1 / ( h c l k d i v + 1 ) 0 1 1 0 1 0 0 0 1 p l l f o u t l x t h x t l i r c 0 0 0 1 1 1 h i r c / 2 1 0 0 h i r c 1 0 1 p l l _ f o u t / 2 a p b 0 p c l k 0 l e g e n d : h i r c = 4 8 m h z h i g h s p e e d i n t e r n a l c l o c k s i g n a l h x t = 4 m h z ~ 2 4 m h z h i g h s p e e d e x t e r n a l c l o c k s i g n a l l i r c = 1 0 k h z l o w s p e e d i n t e r n a l c l o c k s i g n a l l x t = 3 2 . 7 6 8 k h z l o w s p e e d e x t e r n a l c l o c k s i g n a l
nuc121 /125 feb . 23 , 201 7 page 97 of 150 rev 1 .0 0 nuc121 /125 series datasheet figure 6.3 - 4 hxt stop protect procedure except hxt fail (stop) detect or , hxt also has a frequency detector to observe hxt clock frequncy if normally and it also ha s individual enable (hxtfqden=clk_clkdctl[16]) and interrupt control ( hxtfqi en=clk_c lkdctl[17 ]) . when hxt frequency detector is enabled, the hirc clock is enabled automatically. otherwise, before hxt frequency detector is enabled , we need set the frequency detector upper boundary(uperbd=clk_cdupb[9:0]) and lower boundary ( lowerbd=clk_cdlow b[9:0]) . if hxt clock frequency abnormally condition is detected, the hxtf q if(clk_clkdsts[ 8 ]) is set to 1 and chip will enter interrupt if hxtf q ie n (clk_clkdctl[ 17 ]) is set to 1. different with hxt fail (stop) detect or, w hen hxt clock frequency abnormally condition is detected, the system clock will not auto switch to hirc /2 (24 mhz) even though system clock source come s from hxt or system clock source comes from pll with hxt as the input of pll. the hxt frequency detect or just reminds user hxt clock frequency abnormally through to observe hxtf q if (clk_clkdsts[ 8 ]) . the clock source of systick in cortex ? - m 0 core can use cpu clock or external clock (syst_ ctrl [2]). if using external clock, the systick clock (stclk) has 5 clock sources. the clock source switch depends on the setting of the register stclksel (clk_clksel0[5:3]). the block diagram is shown in figure 6.3 - 5 s e t h x t f d e n t o e n a b l e h x t c l o c k d e t e c t o r h x t f i f = 1 ? s y s t e m c l o c k s o u r c e = h x t o r p l l w i t h h x t ? y e s s y s t e m c l o c k k e e p o r i g i n a l c l o c k n o y e s s w i t c h s y s t e m c l o c k t o h i r c / 2 ( 2 4 m h z ) n o
nuc121 /125 feb . 23 , 201 7 page 98 of 150 rev 1 .0 0 nuc121 /125 series datasheet figure 6.3 - 5 systick clock control block diagram 6.3.4 peripherals clock the peripherals clock had different clock source switch setting, which depends on the different peripheral. 6.3.5 power - down mode clock when entering power - down mode, system clocks, some clock sources, and some peripheral clocks are disabled. some clock sources and peripherals clock are still active in power - down mode. for theses clocks, which still keep active, are listed below: ? clock generator ? 10 khz internal low - speed rc oscillator (lirc ) clock ? 32.768 khz external low - speed crystal oscillator ( l xt ) clock ? peripherals clock (when the modules adopt lxt or lirc as clock source) 6.3.6 clock output this device is equipped with a power - of - 2 frequency divider which is composed by16 chained divide - by - 2 shift registers. one of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to clko function pin. therefore there are 16 options of power - of - 2 divided clocks with the frequency from f in /2 1 to f in /2 16 where f in is input clock frequency to the clock divider. the output formula is f out = f in /2 (n+1) , where f in is the input clock frequency, f out is the clock divider output frequency and n is the 4 - bit value in freqsel (clk_clkoctl[3:0]). when writing 1 to clkoen (clk_clkoctl[4]), the chained counter starts to count. when writing 0 to clkoen (clk_ clkoctl[4]), the chained counter continuously runs till divided clock reaches low state and stay in low state. 1 1 1 0 1 1 0 1 0 0 0 1 h x t l x t h x t h c l k s t c l k s e l ( c l k _ c l k s e l 0 [ 5 : 3 ] ) s t c l k h i r c / 2 0 0 0 1 / 2 1 / 2 1 / 2 l e g e n d : h i r c = 4 8 m h z h i g h s p e e d i n t e r n a l c l o c k s i g n a l h x t = 4 m h z ~ 2 4 m h z h i g h s p e e d e x t e r n a l c l o c k s i g n a l l i r c = 1 0 k h z l o w s p e e d i n t e r n a l c l o c k s i g n a l l x t = 3 2 . 7 6 8 k h z l o w s p e e d e x t e r n a l c l o c k s i g n a l
nuc121 /125 feb . 23 , 201 7 page 99 of 150 rev 1 .0 0 nuc121 /125 series datasheet figure 6.3 - 6 clock source of clock output figure 6.3 - 7 clock output block diagram 0 1 1 0 1 0 0 0 1 0 0 0 h c l k l x t h x t h i r c / 2 c l k o s e l ( c l k _ c l k s e l 2 [ 4 : 2 ] ) c l k o c k e n ( c l k _ a p b c l k 0 [ 6 ] ) c l k o _ c l k 1 1 1 1 0 1 h i r c u s b _ s o f _ d e t l e g e n d : h i r c = 4 8 m h z h i g h s p e e d i n t e r n a l c l o c k s i g n a l h x t = 4 m h z ~ 2 4 m h z h i g h s p e e d e x t e r n a l c l o c k s i g n a l l i r c = 1 0 k h z l o w s p e e d i n t e r n a l c l o c k s i g n a l l x t = 3 2 . 7 6 8 k h z l o w s p e e d e x t e r n a l c l o c k s i g n a l 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 : : 1 6 t o 1 m u x 1 / 2 1 / 2 2 1 / 2 3 1 / 2 1 5 1 / 2 1 6 . . . f r e q s e l ( c l k _ c l k o c t l [ 3 : 0 ] ) c l k o c l k o _ c l k 1 6 c h a i n e d d i v i d e - b y - 2 c o u n t e r c l k o e n ( c l k _ c l k o c t l [ 4 ] ) e n a b l e d i v i d e - b y - 2 c o u n t e r
nuc121 /125 feb . 23 , 201 7 page 100 of 150 rev 1 .0 0 nuc121 /125 series datasheet flash memory controller (fmc) 6.4 6.4.1 overview the n uc 121 /125 series is equipped with 32 k - bytes on - chip embedded flash for application and data flash to store some application dependent data. a user configuration block provides for system initialization. a 4 .5 k - bytes loader rom (ldrom) is used for in - system - programming (isp) function. a 512 by tes security protection rom (sprom) can conceal user program. this chip also supports in - application - programming (iap) function, user switches the code executing without the chip reset after the embedded flash updated. 6.4.2 features ? supports 32 k - bytes applica tion rom (aprom). ? supports 4.5 k - bytes loader rom (ldrom). ? supports c onfigurable data flash size to share with aprom. ? supports 512 bytes security protection rom (sprom) to conceal user program. ? supports 12 bytes user configuration block to control system initialization. ? supports 512 bytes page erase for all embedded flash. ? supports crc - 32 checksum calculation function (must be 512 bytes page alignment) . ? supports aprom, ldrom and embedded sram remap to system vector memory. ? supports in - system - programming (i sp) / in - application - programming (iap) to update embedded flash memory.
nuc121 /125 feb . 23 , 201 7 page 101 of 150 rev 1 .0 0 nuc121 /125 series datasheet general purpose i/o (gpio) 6.5 6.5.1 overview the nuc121 /125 series has up to 52 general purpose i/o pins to be shared with other function pins depending on the chip configuration. these 52 pin s are arranged in 6 ports named as pa, pb, pc, pd, pe and pf. pa has 6 pins on port (pa.10 ~ pa.15). pb has 15 pins on port (pb.0 ~ pb.15, exclude pb.11) . pc has 12 pins on port (pc.0 ~ pc.13, exclude pc.6, pc.7). pd has 10 pins on port (pd.0 ~ pd.11, exclude pd.6, pd.7). pe has 3 pins on port (pe.0 ~ pe.2). pf has 6 pins on port (pf.0 ~ pf.5). each of the 52 pins is independent and has the corresponding register bits to control the pin mode function and data the i/o type of each of i/o pins can be c onfigured by software individually as input, push - pull output, open - drain output or quasi - bidirectional mode. after the chip is reset, the i/o mode of all pins are depending on cioin (config0[10]). each i/o pin has a very weakly individual pull - up resistor which is about 110 k ? ~ 300 k ? for v dd is from 5.0 v to 2.5 v. 6.5.2 features ? four i/o modes: ? quasi - bidirectional mode ? push - pull output mode ? open - drain output mode ? input mode ? ttl/schmitt trigger input selectable ? i/o pin can be configured as interrupt source with edge/level setting ? supports high slew rate i/o mode ? supports high drive strength mode for port c ? configurable default i/o mode of all pins after reset by cioini (config0[10]) setting ? cioin = 0, all gpio pins in input mode after chip reset ? cioin = 1, a ll gpio pins in quasi - bidirectional mode after chip reset ? i/o pin internal pull - up resistor enabled only in quasi - bidirectional i/o mode ? enabling the pin interrupt function will also enable the wake - up function
nuc121 /125 feb . 23 , 201 7 page 102 of 150 rev 1 .0 0 nuc121 /125 series datasheet pdma controller (pdma) 6.6 6.6.1 overview the peripheral direct memory access (pdma) controller is used to provide high - speed data transfer. the pdma controller can transfer data from one address to another without cpu intervention. this has the benefit of reducing the workload of cpu and keeps cpu re sources free for other applications. the pdma controller has a total of 5 channels and each channel can perform transfer between memory and peripherals or between memory and memory. the pdma supports time - out function for channel 0 and channel 1. 6.6.2 features ? supports 5 independently configurable channels ? supports selectable 2 level of priority (fixed priority or round - robin priority) ? supports transfer data width of 8, 16, and 32 bits ? supports source and destination address increment size can be byte, half - word , word or no increment ? supports software and spi, uart, i 2 s, i 2 c, usci, adc , pwm and timer request ? supports scatter - gather mode to perform sophisticated transfer through the use of the descriptor link list table ? supports single and burst transfer type ? sup ports time - out function for channel 0 and channel 1
nuc121 /125 feb . 23 , 201 7 page 103 of 150 rev 1 .0 0 nuc121 /125 series datasheet timer controller (tmr) 6.7 6.7.1 overview the timer controller includes four 32 - bit timers, timer0 ~ timer3, allowing user to easily implement a timer control for applications. the timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins. 6.7.2 features ? four sets of 32 - bit timers with 24 - bit up counter and one 8 - bit prescale counter ? independ ent clock source for each timer ? provides one - shot, periodic, toggle - output and continuous counting operation modes ? 24 - bit up counter value is readable through cnt ( timerx_cnt[23:0] ) ? support s event counting function ? 24 - bit capture value is readable through capdat ( timerx_cap[23:0] ) ? supports external capture pin event f or interval measurement ? supports external capture pin event to reset 24 - bit up counter ? supports chip wake - up from idle/power - down mode if a timer interrupt signal is generated ? support timer0 ~ timer3 time - out interrupt signal or capture interrupt signal to trigger pwm, bpwm, pdma, adc and dac function
nuc121 /125 feb . 23 , 201 7 page 104 of 150 rev 1 .0 0 nuc121 /125 series datasheet basic pwm generator and capture timer (bpwm) 6.8 6.8.1 overview the nuc121 /125 series provides two bpwm generators : bpwm0 and bpwm1. each bpwm supports 6 channels of bpwm output or input capture. there is a 12 - bit prescaler to support flexible clock to the 16 - bit bpwm counter with 16 - bit comparator. the bpwm counter supports up, down and up - down counter types, all 6 channels share one counter. bpwm uses th e comparator compared with counter to generate events. these events are used to generate bpwm pulse, interrupt and trigger signal for adc to start conversion. for bpwm output control unit, it supports polarity output, independent pin mask and tri - state out put enable. the bpwm generator also supports input capture function to latch bpwm counter value to corresponding register when input channel has a rising transition, falling transition or both transition is happened. 6.8.2 features bpwm function features 6.8.2.1 ? supports maximum clock frequency up to100 mhz ? supports up to two bpwm modules, each module provides 6 output channels ? supports independent mode for bpwm output/capture input channel ? supports 12 - bit pre - scalar from 1 to 4096 ? supports 16 - bit resolution bpwm counter, each module provides 1 bpwm counter ? up, down and up/down counter operation type ? supports mask function and tri - state enable for each bpwm pin ? supports interrupt on the following events: ? bpwm counter match zero, period value or compared value ? suppo rts trigger adc on the following events: ? bpwm counter match zero, period value or compared value capture function features 6.8.2.2 ? supports up to 12 c apture input channels with 16 - bit resolution ? supports rising edge or falling edge or both edges capture condition ? supports input rising/falling edge or both edges capture interrupt ? supports rising/falling or both edges capture with counter reload option
nuc121 /125 feb . 23 , 201 7 page 105 of 150 rev 1 .0 0 nuc121 /125 series datasheet pwm generator and capture timer (pwm) 6.9 6.9.1 overview the nuc121 /125 series provides two pwm generators pwm0 and pwm1. each pwm supports 6 channels of pwm output or input capture. there is a 12 - bit prescaler to support flexible clock to the 16 - bit pwm counter with 16 - bit comparator. the pwm counter supports up, down and up - down counter types. pwm uses the c omparator compared with counter to generate events. these events are used to generate pwm pulse, interrupt and trigger signal for adc to start conversion. the pwm generator supports two standard pwm output modes: independent mode and complementary mode, wh ich have difference architecture. in complementary mode, there are two comparators to generate various pwm pulse with 12 - bit dead - time generator. for pwm output control unit, it supports polarity output, independent pin mask, tri - state output enable and br ake functions. the pwm generator also supports input capture function to latch pwm counter value to the corresponding register when input channel has a rising transition, falling transition or both transition is happened. 6.9.2 features pwm function features 6.9.2.1 ? sup ports maximum clock frequency up to100 mhz ? supports up to two pwm modules, each module provides 6 output channels ? supports independent mode for pwm output/capture input channel ? supports complementary mode for 3 complementary paired pwm output channel ? dead - time insertion with 12 - bit resolution ? two compared values during one period ? supports 12 - bit pre - scalar from 1 to 4096 ? supports 16 - bit resolution pwm counter, each module provides 3 pwm counters ? up, down and up/down counter operation type ? supports mask function and tri - state enable for each pwm pin ? supports brake function ? brake source from pin and system safety events (clock failed, brown - out detection and cpu lockup) ? noise filter for brake source from pin ? edge detect brake source to control brake state until brake interrupt cleared ? level detect brake source to auto recover function after brake condition removed ? supports interrupt on the following events: ? pwm counter match zero, period value or compared value ? brake condition happened ? supports trigger adc on the following events: ? pwm counter match zero, period value or compared value
nuc121 /125 feb . 23 , 201 7 page 106 of 150 rev 1 .0 0 nuc121 /125 series datasheet capture function features 6.9.2.2 ? supports up to 12 c apture input channels with 16 - bit resolution ? supports rising or falling capture condition ? supports input rising/falling capture i nterrupt ? supports rising/falling capture with counter reload option
nuc121 /125 feb . 23 , 201 7 page 107 of 150 rev 1 .0 0 nuc121 /125 series datasheet watchdog timer (wdt) 6.10 6.10.1 overview the purpose of watchdog timer (wdt) is to perform a system reset when system runs into an unknown state. this prevents system from hanging for an infinite period of time. besides, this watchdog timer supports the function to wake - up system from idle/power - down mode. 6.10.2 features ? 18 - bit free running up counter for wdt time - out interval . ? selectable time - out interval (2 4 ~ 2 18 ) and the time - out interval is 1.6 ms ~ 26. 214 s if wdt_clk = 10 khz . ? system kept in reset state for a period of (1 / wdt_clk) * 63 . ? supports selectable wdt reset delay period, including 1026 , 130 , 18 or 3 wdt_clk reset delay period . ? supports to force wdt enabled after chip powered on or reset by setting cwdten[2:0] in config0 register . ? supports wdt time - out wake - up function only if wdt clock source is selected as lirc or lxt .
nuc121 /125 feb . 23 , 201 7 page 108 of 150 rev 1 .0 0 nuc121 /125 series datasheet window watchdog timer (wwdt) 6.11 6.11.1 overview the window watchdog timer (wwdt) is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 6.11.2 features ? 6 - bit down counter value cntdat (wwdt_cnt[5:0]) and maximum 6 - bit compare value cmpdat (wwdt_ctl[21:16]) to make the wwdt time - out window period flexible ? supports 4 - bit value pscsel (wwdt_ctl[11:8]) to programmable maximum 11 - bit prescale counter period of wwdt counter ? wwdt counter suspends in idle/power - down mode ? wwdt counter only can be reload ed within in valid window period to prevent system reset
nuc121 /125 feb . 23 , 201 7 page 109 of 150 rev 1 .0 0 nuc121 /125 series datasheet usci - universal serial control interface controller 6.12 6.12.1 overview the universal serial control interface (usci) is a flexible interface module covering several serial communication protocols. the user c an configure this controller as uart, spi, or i 2 c functional protocol. 6.12.2 features the controller can be individually configured to match the application needs. the following protocols are supported: ? uart ? spi ? i 2 c to increase readability, the registers of usci have different alias names that depending on the selected protocol. for example, register usci_ctl has alias name uuart _ctl for protocol uart, has alias name uspi _ctl for protocol spi, and has alias name ui2c _ctl for protocol i 2 c.
nuc121 /125 feb . 23 , 201 7 page 110 of 150 rev 1 .0 0 nuc121 /125 series datasheet usci - uart m ode 6.13 6.13.1 overvie w the asynchronous serial channel uart covers the reception and the transmission of asynchronous data frames . it performs a serial - to - parallel conversion on data received from the peripheral, and a parallel - to - serial conversion on data transmitted from the controller. the receiver and transmitter are independent, frames can start at different points in time for transmission and reception. the uart controller also provides auto flow control . there are two conditions to wake - up the system by incoming data or ncts . 6.13.2 features ? supports one transmit buffer and two receive buffer for data payload ? supports hardware auto flow control function ? supports programmable baud - rate generator ? support s 9 - bit data transfer (9 - bit rs - 485) ? supports b aud rate detection by built - in capture event of baud rate generator ? supports pdma capability ? supports wake - up function (data and ncts wakeup only)
nuc121 /125 feb . 23 , 201 7 page 111 of 150 rev 1 .0 0 nuc121 /125 series datasheet usci - spi m ode 6.14 6.14.1 overview the spi protocol of usci controller applies to synchronous serial data communication and allows full duplex transfer. it supports both m aster and s lave operation m ode with the 4 - wire bi - direction interface. spi mode of usci controller perform s a serial - to - parallel conversion on data received from a peripheral device, and a parallel - to - seri al conversion on data transmitted to a peripheral device. the spi mode is selected by funmode (uspi_ctl[2:0]) = 0x1 this spi protocol can operate as m aster or s lave mode by setting the slave ( uspi_protctl [ 0 ]) to communicate with the off - chip spi s lave or m aster device. the application block diagrams in m aster and s lave mode are shown below. note: x = 0 figure 6.14 - 1 spi master mode application block diagram note: x = 0 figure 6.14 - 2 spi slave mode application block diagram 6.14.2 features ? supports master or slave mode operation (the maximum frequency for master = f pclk / 2, for slave < f pclk / 5) s p i s l a v e d e v i c e m a s t e r t r a n s m i t d a t a m a s t e r r e c e i v e d a t a s e r i a l b u s c l o c k s l a v e s e l e c t s p i _ m o s i ( u s c i x _ d a t 0 ) s p i _ m i s o ( u s c i x _ d a t 1 ) s p i _ c l k ( u s c i x _ c l k ) s p i _ s s ( u s c i x _ c t l ) s p i _ m o s i s p i _ m i s o u s c i s p i m a s t e r u s c i s p i m a s t e r s p i _ c l k s p i _ s s s p i m a s t e r d e v i c e s l a v e r e c e i v e d a t a s l a v e t r a n s m i t d a t a s e r i a l b u s c l o c k s l a v e s e l e c t s p i _ m o s i ( u s c i x _ d a t 0 ) s p i _ m i s o ( u s c i x _ d a t 1 ) s p i _ c l k ( u s c i x _ c l k ) s p i _ s s ( u s c i x _ c t l ) s p i _ m o s i s p i _ m i s o u s c i s p i s l a v e u s c i s p i s l a v e s p i _ c l k s p i _ s s
nuc121 /125 feb . 23 , 201 7 page 112 of 150 rev 1 .0 0 nuc121 /125 series datasheet ? configurable bit length of a transfer word from 4 to 16 - bit ? supports one transmit buffer and two receive buffers for data payload ? supports msb first or lsb first transfer sequence ? supports w ord s uspend function ? supports pdma transfer ? supports 3 - wire, no slave select signal, bi - direction interface ? supports wake - up function by slave select signal in slave mode ? supports one data channel half - duplex transfer
nuc121 /125 feb . 23 , 201 7 page 113 of 150 rev 1 .0 0 nuc121 /125 series datasheet usci - i 2 c m ode 6.15 6.15.1 overview on i 2 c bus, data is transferred between a master and a slave. data bits transfer on the scl and sda lines are synchronously on a byte - by - byte basis. each data byte is 8 - bit. there is one scl clock pulse for each data bit with the msb being transmitted first, and an acknowledge bit follows each transferred byte. each bit is sampled during the high period of scl; therefore , the sda line may be changed only during the low period of scl and must be held stable during the high period of scl. a transition on the sda line while scl is high is interpreted as a command (start or s top). please refer to figure 6.15 - 1 for more detailed i 2 c bus timing. figure 6.15 - 1 i 2 c bus timing the devices on - chip i 2 c provides the serial interface that meets the i 2 c bus standard mode specification. the i 2 c port handles byte transfers autonomously. the i 2 c mode is selected by funmode (ui2c_ctl [2:0]) = 100 b . when enable this port, t he usci interfaces to the i 2 c bus via two pins: sda and scl. when i/o pins are used as i 2 c ports, user must set the pins function to i 2 c in advance. note: pull - up resistor is needed for i 2 c operation because the sda and scl are set to open - drain pins when usci is selected to i 2 c operation mode . 6.15.2 features ? full master and slave device capability ? supports of 7 - bit addressing, as well as 10 - bit addressing ? communication in standard mode (100 kbit/s) or in fast mode (up to 400 kbit/s) ? suppor ts multi - master bus ? supports 10 - bit bus time - out capability ? supports bus monitor mode. ? supports power down wake - up by data toggle or address match ? supports setup/hold time programmable ? supports multiple address recognition (two slave address with mask opti on) t b u f s t o p s d a s c l s t a r t t h d _ s t a t l o w t h d _ d a t t h i g h t f t s u _ d a t r e p e a t e d s t a r t t s u _ s t a t s u _ s t o s t o p t r ( u s c i _ d a t 0 ) ( u s c i _ c l k )
nuc121 /125 feb . 23 , 201 7 page 114 of 150 rev 1 .0 0 nuc121 /125 series datasheet uart interface controller (uart) 6.16 6.16.1 overview the nuc121 /125 series provides one channel of universal asynchronous receiver/transmitters (uart). uart controller performs normal speed uart and supports flow control function. the uart controller performs a serial - to - parallel conversion on data received from the perip heral and a parallel - to - serial conversion on data transmitted from the cpu. each uart controller channel supports ten types of interrupts. the uart controller also supports irda sir, lin and rs - 485 function modes and auto - baud rate measuring function. 6.16.2 feat ures ? full - duplex asynchronous communications ? supports maximum clock frequency up to 10 mbps ? separate s receive and transmit 16/16 bytes entry fifo for data payloads ? support s hardware auto - flow control ? programmable receiver buffer trigger level ? support s programmable baud rate generator for each channel individually ? support s n cts , incoming data, received data fifo reached threshold and rs - 485 address match (aad mode) wake - up function ? support s 8 - bit receiver buffer time - out detection function ? programmable transmitting data delay time between the last stop and the next start bit by setting dly ( uart_tout [ 15:8 ] ) ? supports auto - baud rate measurement and baud rate compensation function ? support s break error, frame error, parity error and receiv e/ transmit buffer overflow detect ion function ? fully programmable serial - interface characteristics ? programmable number of data bit, 5 - , 6 - , 7 - , 8 - bit character ? programmable parity bit, even, odd, no parity or stick parity bit generation and detection ? programmable stop bit, 1, 1.5, or 2 stop bit generation ? support s irda sir function mode ? supports for 3/16 bit duration for normal mode ? support s lin function mode ? supports lin master/slave mode ? supports programmable break generation function for transmitter ? supports break detection function for receiver ? support s rs - 485 function mode ? supports rs - 485 9 - bit mode ? supports hardware or software enables to program nrts pin to control rs - 485 transmission direction
nuc121 /125 feb . 23 , 201 7 page 115 of 150 rev 1 .0 0 nuc121 /125 series datasheet ? support s pdma transfer function
nuc121 /125 feb . 23 , 201 7 page 116 of 150 rev 1 .0 0 nuc121 /125 series datasheet i 2 c serial interface controller (i 2 c ) 6.17 6.17.1 overview i 2 c is a two - wire, bi - directional serial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. there are two sets of i 2 c controller s which support power - down wake - up func tion. 6.17.2 features the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the i 2 c bus include: ? supports up to two i 2 c ports ? supports speed up to 1mbps ? master/slave mode ? bidirectional data tr ansfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allow devices with different bit rates to communicate via one serial bus ? serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer ? built - in 14 - bit time - out counter requesting the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows ? programmable clocks allow for versatile rate control ? supports 7 - bit addressing mode ? supports multiple address recognition ( four slave address with mask option) ? supports power - down wake - up function ? supports pdma with one buffer capability ? supports two - level buffer function ? sup ports setup/hold time programmable
nuc121 /125 feb . 23 , 201 7 page 117 of 150 rev 1 .0 0 nuc121 /125 series datasheet serial peripheral interface (spi) 6.18 6.18.1 overview the serial peripheral interface (spi) applies to synchronous serial data communication and allows full duplex transfer. devices communicate in master/slave mode with the 4 - wire b i - direction interface. the nuc121 /125 series contains one spi controller performing a serial - to - parallel conversion on data received from a peripheral device, and a parallel - to - serial conversion on data transmitted to a peripheral device. the spi controlle r can be configured as a master or a slave device. this controller also supports the pdma function to access the data buffer. the spi controller also support s i 2 s mode to connect external audio codec. 6.18.2 features ? spi mode ? one set of spi controller ? supports master or slave mode operation ? configurable bit length of a transaction word from 8 to 32 - bit ? provides separate 4 - level depth transmit and receive fifo buffers ? supports msb first or lsb first transfer sequence ? supports byte reorder function ? supports pdma t ransfer ? supports one data channel half - duplex transfer ? support receive - only mode ? i 2 s mode ? supports master or slave ? capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes ? provides separate 4 - level depth transmit and receive fifo buffers ? supports monaural an d stereo audio data ? supports pcm mode a, pcm mode b, i 2 s and msb justified data format ? supports pdma transfer
nuc121 /125 feb . 23 , 201 7 page 118 of 150 rev 1 .0 0 nuc121 /125 series datasheet usb device controller (usbd) 6.19 6.19.1 overview there is one set of usb 2.0 full - speed device controller and transceiver in this device. it is compliant with usb 2.0 full - speed device specification and supports control/bulk/interrupt/isochronous transfer types. it implements a full - speed (12 mbit/s) function interface with added support for usb 2.0 link power management. in this device controller, there ar e two main interfaces: the apb bus and usb bus which comes from the usb phy transceiver. for the apb bus, the cpu can program control registers through it. there are 768 bytes internal sram as data buffer in this controller. for in or out transfer, it is n ecessary to write data to sram or read data from sram through the apb interface or sie. user needs to set the effective starting address of sram for each endpoint buffer through buffer segmentation register (usbd_bufsegn, n=0~7). there are 8 endpoints in this controller. each of the endpoint can be configured as in or out endpoint. all the operations including control, bulk, interrupt and isochronous transfer are implemented in this block. the block of e ndpoint c ontrol is also used to manag e the data sequential synchronization, endpoint states, current start address, transaction status, and data buffer status for each endpoint. there are five different interrupt events in this controller. they are the sof event, no - event - wake - up, device plug - in or plug - out event, usb events, like in ack, out ack etc, and bus events, like suspend and resume, etc. any event will cause an interrupt, and users just need to check the related event flags in interrupt event status register (usbd_intsts) to acknowled ge what kind of interrupt occurring, and then check the related usb endpoint status register (usbd_epsts) to acknowledge what kind of event occurring in this endpoint. a software - disconnect function is also supported for this usb controller. it is used to simulate the disconnection of this device from the host. if user enables se0 bit (usbd_se0), the usb controller will force the output of usb_d+ and usb_d - to level low and its function is disabled. after disable the se0 bit, host will enumerate the usb dev ice again. for more information on the universal serial bus, please refer to universal serial bus specification revision 1.1. 6.19.2 features ? compliant with usb 2.0 full - speed specification ? provides 1 interrupt vector with 5 different interrupt events ( nev wk, vb usdet, usb , bus and sof ) ? supports control/bulk/interrupt/isochronous transfer type ? supports suspend function when no bus activity existing for 3 ms ? supports 8 endpoints for configurable control/bulk/interrupt/isochronous transfer types and maximum 768 byte s buffer size ? provides remote wake - up capability ? start of frame (sof) locked clock pulse generation ? s upport s usb 2.0 l ink p ower management
nuc121 /125 feb . 23 , 201 7 page 119 of 150 rev 1 .0 0 nuc121 /125 series datasheet analog - to - digital converter (adc) 6.20 6.20.1 overview the nuc121 /125 series contains one 12 - bit successive approximation analog - to - digital converter (sar a/d converter) with 14 input channels. the a/d converter supports four operation modes: single, burst, single - cycle scan and continuous scan mode. the a/d converter can b e started by software, external pin (stadc/pc.8), timer0~3 overflow pulse trigger and pwm trigger. 6.20.2 features ? analog input voltage range: 0 ~ av dd . ? 12 - bit resolution and 10 - bit accuracy is guaranteed ? up to 12 single - end analog input channels or 6 differenti al analog input channels ? maximum adc peripheral clock frequency is 16 mhz ? up to 800k sps sampling rate ? configurable adc internal sampling time ? four operation modes: ? single mode: a/d conversion is performed one time on a specified channel. ? burst mode: a/d converter samples and converts the specified single channel and sequentially stores the result in fifo. ? single - cycle scan mode: a/d conversion is performed only one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel. ? continuous scan mode: a/d converter continuously performs single - cycle scan mode until software stops a/d conversion. ? an a/d conversion can be started by: ? software write 1 to adst bit ? external pin (stadc) ? timer 0~3 overflow puls e trigger ? pwm trigger with optional start delay period ? each conversion result is held in data register of each channel with valid and overrun indicators. ? conversion result can be compared with specified value and user can select whether to generate an inte rrupt when conversion result matches the compare register setting. ? two internal channels which are band - gap voltage (vbg) and temperature sensor (vtemp). ? support s pdma transfer mode. note 1 : adc sampling rate = (adc peripheral clock frequency) / (total adc conversion cycle) note 2 : if the internal channel (vtemp) is selected to convert, the sampling rate needs to be less than 300k sps for accurate result.
nuc121 /125 feb . 23 , 201 7 page 120 of 150 rev 1 .0 0 nuc121 /125 series datasheet 7 application circuit a v s s a v d d a v c c d v c c v s s v d d 0 . 1 u f f b f b d v c c 1 0 u f / 2 5 v 1 0 k p o w e r r e s e t c i r c u i t n r e s e t l d o _ c a p n u c 1 2 1 s e r i e s v d d v s s n r e s e t i c e _ d a t i c e _ c l k s w d i n t e r f a c e 1 u f v d d v s s i 2 c d e v i c e c l k d i o i 2 c x _ s d a i 2 c x _ s c l 4 . 7 k v d d v s s s p i d e v i c e c s c l k m i s o s p i x _ s s m o s i s p i x _ c l k s p i x _ m i s o s p i x _ m o s i l d o r s 2 3 2 t r a n s c e i v e r r o u t t i n r i n t o u t p c c o m p o r t 0 . 1 u f d v c c 4 . 7 k d v c c d v c c n o t e : f o r t h e s p i d e v i c e , t h e c h i p s u p p l y v o l t a g e m u s t b e e q u a l t o s p i d e v i c e w o r k i n g v o l t a g e . f o r e x a m p l e , w h e n t h e s p i f l a s h w o r k i n g v o l t a g e i s 3 . 3 v , t h e n u c 1 2 1 c h i p s u p p l y v o l t a g e m u s t a l s o b e 3 . 3 v . u a r t [ 1 ] u a r t x _ r x d u a r t x _ t x d u s b f s d e v i c e u s b _ v d d 3 3 _ c a p 1 u f u s b _ d - u s b _ d + u s b _ i d u s b _ v b u s 3 3 3 3
nuc121 /125 feb . 23 , 201 7 page 121 of 150 rev 1 .0 0 nuc121 /125 series datasheet a v s s a v d d a v c c d v c c 1 v s s v d d 0 . 1 u f f b f b d v c c 1 0 u f / 2 5 v 1 0 k p o w e r r e s e t c i r c u i t n r e s e t l d o _ c a p n u c 1 2 5 s e r i e s v d d v s s n r e s e t i c e _ d a t i c e _ c l k s w d i n t e r f a c e 1 u f v d d v s s i 2 c d e v i c e c l k d i o i 2 c x _ s d a i 2 c x _ s c l 4 . 7 k v d d v s s s p i d e v i c e c s c l k m i s o s p i x _ s s m o s i s p i x _ c l k s p i x _ m i s o s p i x _ m o s i l d o r s 2 3 2 t r a n s c e i v e r r o u t t i n r i n t o u t p c c o m p o r t 0 . 1 u f d v c c 2 4 . 7 k d v c c 2 d v c c 1 n o t e 1 : f o r t h e s p i d e v i c e , t h e c h i p s u p p l y v o l t a g e m u s t b e e q u a l t o s p i d e v i c e w o r k i n g v o l t a g e i f s p i x _ s s , s p i x _ c l k , s p i x _ m i s o a n d s p i x _ m o s i a r e n o t i n v d d i o d o m a i n . f o r e x a m p l e , w h e n t h e s p i f l a s h w o r k i n g v o l t a g e i s 3 . 3 v , t h e n u c 1 2 5 c h i p s u p p l y v o l t a g e m u s t a l s o b e 3 . 3 v . u a r t [ 1 ] u a r t x _ r x d u a r t x _ t x d u s b f s d e v i c e u s b _ v d d 3 3 _ c a p 1 u f u s b _ d - u s b _ d + u s b _ i d u s b _ v b u s 3 3 3 3 v d d i o d v c c 2 [ 2 ] n o t e 2 : d v c c 2 c a n b e 1 . 8 v ~ 5 . 5 v .
nuc121 /125 feb . 23 , 201 7 page 122 of 150 rev 1 .0 0 nuc121 /125 series datasheet 8 electrical character istics absolute maximum ratings 8.1 symbol parameter min max unit dc power supply v dd - v ss - 0.3 +7.0 v input voltage v in v ss C 0.3 v dd + 0.3 v input voltage on v ddio v ddio +1.8 +5.5 v oscillator frequency 1/t clcl 4 24 mhz operating temperature t a - 40 +105 ? c storage temperature t st - 55 +150 ? c maximum current into v dd i dd - 120 ma maximum current out of v ss i ss - 120 ma maximum current sunk by a i/o pin i io - 35 ma maximum current sourced by a i/o pin - 35 ma maximum current sunk by total i/o pins - 100 ma maximum current sourced by total i/o pins - 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the lift and reliability of th e device.
nuc121 /125 feb . 23 , 201 7 page 123 of 150 rev 1 .0 0 nuc121 /125 series datasheet dc electrical characteristics 8.2 (v dd - v ss = 2.5 ~ 5.5 v, t a = 25 ? c, f osc = 50 mhz unless otherwise specified.) parameter sym. specifications test conditions min. typ. max. unit operation v oltage v dd - v ss 2.5 - 5.5 v v dd = 2.5 ~ 5.5 v up to 50 mhz power supply for pb.14, pa.11, pa.10, pb.4 and pb.5 v ddio - v ss 1.8 - 5.5 v power ground v ss - av ss - 0.05 - +0.05 v ldo output voltage v ldo 1.62 1.8 1.98 v mcu operating in run , idle or power - down mode c ldo 1 - 1 uf connect to ldo_cap pin band - gap voltage v bg - 1.21 - v v dd = 2.5 v ~ 5.5 v, t a = - 40 ~ 105 ? c allowed voltage difference for v dd and av dd v dd - a v dd - 0.3 - +0.3 v operating current normal run mode hclk = 48 mhz while(1){}executed from flash v ldo =1.8 v i dd 1 - 20. 4 - ma v dd hxt hirc pll all digital module 5.5 v 12 mhz x v v i dd 2 - 9. 5 - ma 5.5 v 12 mhz x v x i dd 3 - 20.0 - ma 3.0 v 12 mhz x v v i dd 4 - 9 . 3 - ma 3.0 v 12 mhz x v x operating current normal run mode hclk = 48 mhz while(1){}executed from flash v ldo =1.8 v i dd 5 - 24.6 - ma v dd hxt hirc pll all digital module 5.5 v x 48 mhz v v i dd 6 - 11.5 - ma 5.5 v x 48 mhz v x i dd 7 - 24.1 - ma 3.0 v x 48 mhz v v i dd 8 - 11.4 - ma 3.0 v x 48 mhz v x operating current normal run mode hclk = 48 mhz while(1){}executed from flash v ldo =1.8 v i dd 9 - 20.0 - ma v dd hxt hirc pll all digital module ma 5.5 v 12 mhz x v v i dd 10 - 9.1 - ma 5.5 v 12 mhz x v x i dd 11 - 19.5 - ma 3.0 v 12 mhz x v v i dd 12 - 8.8 - ma 3.0 v 12 mhz x v x operating current i dd 13 - 20.0 - ma v dd hxt hirc pll all digital module
nuc121 /125 feb . 23 , 201 7 page 124 of 150 rev 1 .0 0 nuc121 /125 series datasheet parameter sym. specifications test conditions min. typ. max. unit normal run mode hclk = 48 mhz while(1){}executed from flash v ldo =1.8 v 5.5 v x 48 mhz x v i dd 14 - 8.5 - ma 5.5 v x 48 mhz x x i dd 15 - 19.5 - ma 3.0 v x 48 mhz x v i dd 16 - 8.4 - ma 3.0 v x 48 mhz x x operating current normal run mode hclk = 24 mhz while(1){}executed from flash v ldo =1.8 v i dd 17 - 9.7 - ma v dd hxt hirc pll all digital module 5.5 v 24 mhz x x v i dd 18 - 4.4 - ma 5.5 v 24 mhz x x x i dd 19 - 9.5 - ma 3.0 v 24 mhz x x v i dd 20 - 4.2 - ma 3.0 v 24 mhz x x x operating current normal run mode hclk = 24 mhz while(1){}executed from flash v ldo =1.8 v i dd 21 - 11.1 - ma v dd hxt hirc pll all digital module 5.5 v x 48/2 mhz x v i dd 22 - 5.2 - ma 5.5 v x 48/2 mhz x x i dd 23 - 10.9 - ma 3.0 v x 48/2 mhz x v i dd 24 - 5.1 - ma 3.0 v x 48/2 mhz x x operating current normal run mode hclk = 16 mhz while(1){}executed from flash v ldo =1.8 v i dd 2 5 - 6.4 - ma v dd hxt hirc pll all digital module 5.5 v 16 mhz x x v i dd 2 6 - 3.1 - ma 5.5 v 16 mhz x x x i dd 2 7 - 6.3 - ma 3.0 v 16 mhz x x v i dd 2 8 - 3.0 - ma 3.0 v 16 mhz x x x operating current normal run mode hclk = 16 mhz while(1){}executed from flash v ldo =1.8 v i dd 2 9 - 8.3 - ma v dd hxt hirc pll all digital module 5.5 v x 48/3 mhz x v i dd 30 - 4.2 - ma 5.5 v x 48/3 mhz x x i dd 31 - 8.1 - ma 3.0 v x 48/3 mhz x v i dd 32 - 4.1 - ma 3.0 v x 48/3 mhz x x operating current normal run mode hclk = 12 mhz while(1){}executed from flash v ldo =1.8 v i dd 33 - 4.9 - ma v dd hxt hirc pll all digital module 5.5 v 12 mhz x x v i dd 34 - 2.2 - ma 5.5 v 12 mhz x x x i dd 35 - 4.7 - ma 3.0 v 12 mhz x x v i dd 36 - 2.1 - ma 3.0 v 12 mhz x x x operating current normal run mode i dd 3 7 - 6.8 - ma v dd hxt hirc pll all digital module
nuc121 /125 feb . 23 , 201 7 page 125 of 150 rev 1 .0 0 nuc121 /125 series datasheet parameter sym. specifications test conditions min. typ. max. unit hclk = 12 mhz while(1){}executed from flash v ldo =1.8 v 5.5 v x 48/4 mhz x v i dd 3 8 - 3.7 - ma 5.5 v x 48/4 mhz x x i dd 3 9 - 6.6 - ma 3.0 v x 48/4 mhz x v i dd 40 - 3.6 - ma 3.0 v x 48/4 mhz x x operating current normal run mode hclk = 4 mhz while(1){}executed from flash v ldo =1.8 v i dd 41 - 1.8 - ma v dd hxt hirc pll all digital module 5.5 v 4 mhz x x v i dd 42 - 0.9 - ma 5.5 v 4 mhz x x x i dd 43 - 1.7 - ma 3.0 v 4 mhz x x v i dd 44 - 0.8 - ma 3.0 v 4 mhz x x x operating current normal run mode hclk = 4 mhz while(1){}executed from flash v ldo =1.8 v i dd 4 5 - 3.9 - ma v dd hxt hirc pll all digital module 5.5 v x 48/12 mhz x v i dd 4 6 - 2.5 - ma 5.5 v x 48/12 mhz x x i dd 4 7 - 3.9 - ma 3.0 v x 48/12 mhz x v i dd 4 8 - 2.5 - ma 3.0 v x 48/12 mhz x x operating current normal run mode hclk = 32.768 k hz while(1){}executed from flash v ldo =1.8 v i dd 49 - 120 - u a v dd lxt lirc pll all digital module 5.5 v 32.768 khz x x v i dd 50 - 113 - u a 5.5 v 32.768 khz x x x i dd 51 - 105 - u a 3.0 v 32.768 khz x x v i dd 52 - 98 - u a 3.0 v 32.768 khz x x x operating current normal run mode hclk = 10 k hz while(1){}executed from flash v ldo =1.8 v i dd 53 - 111 - u a v dd lxt lirc pll all digital module 5.5 v x 10 khz x v i dd 54 - 109 - u a 5.5 v x 10 khz x x i dd 55 - 96 - u a 3.0 v x 10 khz x v i dd 56 - 94 - u a 3.0 v x 10 khz x x operating current idle mode hclk = 50 mhz while(1){}executed from flash v ldo =1.8 v i idle 1 - 15.2 - ma v dd hxt hirc pll all digital module 5.5 v 12 mhz x v v i idle 2 - 4.4 - ma 5.5 v 12 mhz x v x i idle 3 - 14.9 - ma 3.0 v 12 mhz x v v i idle 4 - 4.3 - ma 3.0 v 12 mhz x v x operating current idle mode i idle5 - 19.3 - ma v dd hxt hirc pll all digital module
nuc121 /125 feb . 23 , 201 7 page 126 of 150 rev 1 .0 0 nuc121 /125 series datasheet parameter sym. specifications test conditions min. typ. max. unit hclk = 50 mhz while(1){}executed from flash v ldo =1.8 v 5.5 v x 48 mhz v v i idle6 - 6.8 - ma 5.5 v x 48 mhz v x i idle7 - 19.1 - ma 3.0 v x 48 mhz v v i idle8 - 6.8 - ma 3.0 v x 48 mhz v x operating current idle mode hclk = 48 mhz while(1){}executed from flash v ldo =1.8 v i idle9 - 14.7 - ma v dd hxt hirc pll all digital module 5.5 v 12 mhz x v v i idle10 - 4.3 - ma 5.5 v 12 mhz x v x i idle11 - 14.3 - ma 3.0 v 12 mhz x v v i idle12 - 4.1 - ma 3.0 v 12 mhz x v x operating current idle mode hclk = 48 mhz while(1){}executed from flash v ldo =1.8 v i idle13 - 14.5 - ma v dd hxt hirc pll all digital module 5.5 v x 48 mhz x v i idle14 - 3.7 - ma 5.5 v x 48 mhz x x i idle15 - 14.2 - ma 3.0 v x 48 mhz x v i idle16 - 3.6 - ma 3.0 v x 48 mhz x x operating current idle mode hclk = 24 mhz while(1){}executed from flash v ldo =1.8 v i idle17 - 7.2 - ma v dd hxt hirc pll all digital module 5.5 v 24 mhz x x v i idle18 - 2.0 - ma 5.5 v 24 mhz x x x i idle19 - 7.0 - ma 3.0 v 24 mhz x x v i idle20 - 1.8 - ma 3.0 v 24 mhz x x x operating current idle mode hclk = 24 mhz while(1){}executed from flash v ldo =1.8 v i idle21 - 8.3 - ma v dd hxt hirc pll all digital module 5.5 v x 48/2 mhz x v i idle22 - 2.8 - ma 5.5 v x 48/2 mhz x x i idle23 - 8.1 - ma 3.0 v x 48/2 mhz x v i idle24 - 2.75 - ma 3.0 v x 48/2 mhz x x operating current idle mode hclk = 16 mhz while(1){}executed from flash v ldo =1.8 v i idle2 5 - 4.7 - ma v dd hxt hirc pll all digital module 5.5 v 16 mhz x x v i idle2 6 - 1.3 - ma 5.5 v 16 mhz x x x i idle2 7 - 4.6 - ma 3.0 v 16 mhz x x v i idle2 8 - 1.2 - ma 3.0 v 16 mhz x x x operating current idle mode hclk = 16 mhz i idle2 9 - 6.3 - ma v dd hxt hirc pll all digital module 5.5 v x 48/ 3 mhz x v
nuc121 /125 feb . 23 , 201 7 page 127 of 150 rev 1 .0 0 nuc121 /125 series datasheet parameter sym. specifications test conditions min. typ. max. unit while(1){}executed from flash v ldo =1.8 v i idle 30 - 2.6 - ma 5.5 v x 48/3 mhz x x i idle 31 - 6.1 - ma 3.0 v x 48/3 mhz x v i idle 32 - 2.5 - ma 3.0 v x 48/3 mhz x x operating current idle mode hclk = 12 mhz while(1){}executed from flash v ldo =1.8 v i idle33 - 3.6 - ma v dd hxt hirc pll all digital module 5.5 v 12 mhz x x v i idle34 - 1.0 - ma 5.5 v 12 mhz x x x i idle35 - 3.5 - ma 3.0 v 12 mhz x x v i idle36 - 0.9 - ma 3.0 v 12 mhz x x x operating current idle mode hclk = 12 mhz while(1){}executed from flash v ldo =1.8 v i idle37 - 5.2 - ma v dd hxt hirc pll all digital module 5.5 v x 48/4 mhz x v i idle38 - 2.4 - ma 5.5 v x 48/4 mhz x x i idle39 - 5.1 - ma 3.0 v x 48/4 mhz x v i idle40 - 2.4 - ma 3.0 v x 48/4 mhz x x operating current idle mode hclk = 4 mhz while(1){}executed from flash v ldo =1.8 v i idle41 - 1.35 - ma v dd hxt hirc pll all digital module 5.5 v 4 mhz x x v i idle42 - 0.48 - ma 5.5 v 4 mhz x x x i idle43 - 1.28 - ma 3.0 v 4 mhz x x v i idle44 - 0.43 - ma 3.0 v 4 mhz x x x operating current idle mode hclk = 4 mhz while(1){}executed from flash v ldo =1.8 v i idle4 5 - 3.2 - ma v dd hxt hirc pll all digital module 5.5 v x 48/12 mhz x v i idle4 6 - 2.2 - ma 5.5 v x 48/12 mhz x x i idle4 7 - 3.1 - ma 3.0 v x 48/12 mhz x v i idle4 8 - 2.1 - ma 3.0 v x 48/12 mhz x x operating current idle mode hclk = 32.768 k hz while(1){}executed from flash v ldo =1.8 v i idle49 - 116 - u a v dd lxt lirc pll all digital module 5.5 v 32.768 khz x x v i idle50 - 110 - u a 5.5 v 32.768 khz x x x i idle51 - 101 - u a 3.0 v 32.768 khz x x v i idle52 - 95 - u a 3.0 v 32.768 khz x x x operating current idle mode hclk = 10 k hz while(1){}executed from flash i idle53 - 109 - u a v dd lxt lirc pll all digital module 5.5 v x 10 khz x v i idle54 - 107 - u a 5.5 v x 10 khz x x
nuc121 /125 feb . 23 , 201 7 page 128 of 150 rev 1 .0 0 nuc121 /125 series datasheet parameter sym. specifications test conditions min. typ. max. unit v ldo =1.8 v i idle55 - 95 - u a 3.0 v x 10 khz x v i idle56 - 93 - u a 3.0 v x 10 khz x x standby current power - down mode v ldo =1.8 v i pwd1 - 6.7 - u a v dd hxt/hirc lxt /lirc pll ram retention 5.5 v x lxt x v i pwd2 - 6.8 - u a 5.5 v x lirc x v i pwd 3 - 7.4 - u a 5.5 v x lxt & lirc x v i pwd4 - 6. 1 u a 5.5 v x x x v i pwd5 - 5.7 - u a 3.0 v x lxt x v i pwd 6 - 5.8 - u a 3.0 v x lirc x v i pwd 7 - 6.3 - u a 3.0 v x lxt & lirc x v i pwd8 - 5.1 - u a 3.0 v x x x v input current at n reset [1] i in - tbd - ua v dd = 3.3v , v in = 0.45v logic 0 input current (quasi - bidirectional mode) i il - - 68 - ua v dd = v ddio = 5.5v , v in = 0v logic 1 to 0 transition current (quasi - bidirectional mode) [3] i tl - - 600 - ua v dd = v ddio = 5.5v , v in = 2.0 v input pull up resistor r in - 79 - k v dd = v ddio = 5 . 5 v - 143 - k v dd = v ddio = 3.3v - 428 - k v dd = v ddio = 1.8v input leakage current i lk - 0 - ? a v dd = v ddio = 5.5 v, 0 < v in < v dd open - drain or input only mode input low voltage (ttl input) v il1 - 0.3 - 0.8 v v dd = v ddio = 4.5 v - 0.3 - 0.6 v v dd = v ddio = 2 .5 v in put low voltage (ttl input for v ddio domain ) v il2 - 0.58 - v v dd = 2.5 ~ 5.5 v v ddio = 1.8 v input high voltage (ttl input) v ih1 2.0 - v dd + 0.3 v v dd = v ddio = 5 .5 v 1.5 - v dd + 0.3 v v dd = v ddio = 2 .5 v
nuc121 /125 feb . 23 , 201 7 page 129 of 150 rev 1 .0 0 nuc121 /125 series datasheet input high voltage (ttl input for v ddio domain ) v ih2 - 0.64 - v v dd = 2.5 ~ 5.5 v v ddio = 1.8 v input low voltage (schmitt input) v il 3 - 0.3 - 0.3v dd v v dd = v ddio = 2.5 ~ 5.5 v input low voltage (schmitt input for v ddio domain ) v il 4 - 0.3 - 0.3v dd v v ddio = 1.8 ~ 5.5v input high voltage (schmitt input) v ih 3 0.7v dd - v dd + 0.3 v v dd = v ddio = 2.5 ~ 5.5 v input low voltage (schmitt input for v ddio domain ) v ih 4 0.7v ddio - v dd io + 0.3 v v ddio = 1.8 ~ 5.5v hysteresis voltage of pa~pf (schmitt input) v hy - 0.2v dd - v negative going threshold (schmitt input), n reset v il 5 - 0.3 - 0.2v dd v positive going threshold (schmitt i n put), n reset v ih 5 0.8v dd - v dd + 0.3 v internal nreset pin pull up resistor r rst - 17 - k source current (quasi - bidirectional mode) i sr1 - - 390 - u a v dd = v ddio = 4.5 v, v s = 2.4v i sr2 - - 78 - u a v dd = v ddio = 2.7 v, v s = 2.2v i sr3 - - 71 - u a v dd = v ddio = 2.5v, v s = 2.0v source current (quasi - bidirectional mode for v ddio domain ) i sr 4 - 21.2 - u a v dd = 2.5 ~ 5.5 v v ddio = 1.8v, v s = 1.6 v source current (push - pull mode) i sr 5 - - 25 ma v dd = v ddio = 4.5 v, v s = 2.4v i sr 6 - - 5 - ma v dd = v ddio = 2.7v, v s = 2.2 v i sr 7 - - 4 - ma v dd = v ddio = 2.5v, v s = 2.0 v source current ( push - pull mode for v ddio domain ) i s r8 - 1 .5 1 - ma v dd = 2.5 ~ 5.5 v v ddio = 1.8v, v s = 1.6 v sink current (quasi - bidirectional, open - drain and push - i sk1 - 15 - ma v dd = v ddio = 4.5v, v s = 0.45v i sk 2 - 10 - ma v dd = v ddio = 2.7v, v s = 0.45 v
nuc121 /125 feb . 23 , 201 7 page 130 of 150 rev 1 .0 0 nuc121 /125 series datasheet pull mode) i sk 3 - 9 - ma v dd = v ddio = 2.5 v, v s = 0.45 v sink current (quasi - bidirectional, open - drain and push - pull mode for v ddio domain ) i sk 4 - 6.51 - ma v dd = 2.5 ~ 5.5 v v ddio = 1.8v, v s = 1.6 v higher gpio rising rate hiorr 1 - 1.76 - ns v dd = v ddio = 5.5v , without capacitor basic gpio rising rate biorr 1 - 3.12 - ns v dd = v ddio = 5.5v , without capacitor higher gpio rising rate hiorr 2 - 3.73 - ns v dd = v ddio = 3.3 v , without capacitor basic gpio rising rate biorr 2 - 5.97 - ns v dd = v ddio = 3.3 v , without capacitor higher gpio rising rate ( for v ddio domain ) hiorr 3 - 25 - ns v dd = 2.5 ~ 5.5v, v ddio = 1.8 v , without capacitor basic gpio rising rate ( for v ddio domain ) biorr 3 - 27 - ns v dd = 2.5 ~ 5.5v, v ddio = 1.8 v , without capacitor higher gpio falling rate hio f r 1 - 1.53 - ns v dd = v ddio = 5.5v , without capacitor basic gpio falling rate bio f r 1 - 3.02 - ns v dd = v ddio = 5.5v , without capacitor higher gpio falling rate hio f r 2 - 2.84 - ns v dd = v ddio = 3.3 v , without capacitor basic gpio falling rate bio f r 2 - 6.08 - ns v dd = v ddio = 3.3 v , without capacitor higher gpio falling rate ( for v ddio domain ) hio f r 3 - 8.69 - ns v dd = 2.5 ~ 5.5v, v ddio = 1.8 v , without capacitor basic gpio falling rate ( for v ddio domain ) bio f r 3 - 20.28 - ns v dd = 2.5 ~ 5.5v, v ddio = 1.8 v , without capacitor note: 1. n reset pin is a schmitt trigger input. 2. crystal input is a cmos input. 3. all pins can source a transition current when they are externally driven from 1 to 0. in the condition of v dd = 5.5v, the transition current reaches its maximum value when v in approximates to 2v. 4. for ensuring power stability, a 1 uf must be connected between ldo pin and the closest vss pin of the device. also a 100nf bypass capacitor between ldo and vss help suppressing output noise.
nuc121 /125 feb . 23 , 201 7 page 131 of 150 rev 1 .0 0 nuc121 /125 series datasheet ac electrical characteristics 8.3 8.3.1 external 4~24 mhz high speed crystal (hxt) input clock parameter sym. specifications test condition min. typ. max. unit clock high time t chcx 10 - - ns clock low time t clcx 10 - - ns clock rise time t clch 2 - 15 ns clock fall time t chcl 2 - 15 ns input high voltage v ih 0.7v dd - v dd v input low voltage v il 0 - 0.3v dd v note: duty cycle is 50%. 8.3.2 external 4~2 4 mhz high speed crystal (hxt) oscillator parameter sym. specifications test condition min. typ. max. unit oscillator frequency f hxt 4 - 24 mhz v dd = 2 . 5 ~ 5 . 5 v temperature t hxt - 40 - +105 ? c operating current i hxt - 0.74 - m a v dd = 5.5 v @ 12mhz - 0.61 - m a v dd = 3. 3 v @ 12mhz typical crystal application circuits 8.3.2.1 crystal c1 c2 r 1 4mhz ~ 24 mhz 20pf 20pf without t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l v i l v i h
nuc121 /125 feb . 23 , 201 7 page 132 of 150 rev 1 .0 0 nuc121 /125 series datasheet figure 8.3 - 1 typical crystal application circuit 8.3.3 external 32.768 khz low speed crystal (lxt) input clock parameter sym. specifications test condition min. typ. max. unit clock high time t chcx tbd - - ns clock low time t clcx tbd - - ns clock rise time t clch tbd - tbd ns clock fall time t chcl tbd - tbd ns lxt input pin input high voltage xin_v ih 0.7v dd - v dd v lxt input pin input low voltage xin_v il 0 - 0.3v dd v note: duty cycle is 50%. 8.3.4 external 32.768 khz low speed crystal (lxt) oscillator parameter sym. specifications test condition min. typ. max. unit x t _ i n x t _ o u t c 1 r 1 c 2 t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l x i n _ v i l x i n _ v i h
nuc121 /125 feb . 23 , 201 7 page 133 of 150 rev 1 .0 0 nuc121 /125 series datasheet parameter sym. specifications test condition min. typ. max. unit oscillator frequency f lxt - 32.768 - khz v dd = 2.5 ~ 5 . 5 v temperature t lxt - 40 - +105 ? c operating current i lxt 1.15 ? a v dd = 5.5 v - 0.58 - ? a v dd = 3. 3 v typical crystal application circuits 8.3.4.1 crystal c 3 c 4 r 2 32.768 khz 20pf 20pf without figure 8.3 - 2 typical crystal application circuit internal 48 mhz high speed rc oscillator (hirc) 8.3.4.2 parameter sym. specifications test condition min. typ. max. unit supply voltage [1] v hrc 1.62 1.8 1.98 v center frequency f hrc - 48 - mhz t a = 25 ? c , v dd = 3 .3 v calibrated internal oscillator frequency - 2 - + 2 % - 40 ? c ~ + 105 ? c , v dd = 2.5 ~ 5.5 v - 0. 2 5 - + 0. 2 5 % - 40 ? c ~ + 105 ? c , v dd = 2.5 ~ 5.5 v enable 32.768k crystal oscillator or usb sof, and set sys_irctctl[1:0]=10 x t _ i n x t _ o u t c 3 r 2 c 4
nuc121 /125 feb . 23 , 201 7 page 134 of 150 rev 1 .0 0 nuc121 /125 series datasheet parameter sym. specifications test condition min. typ. max. unit operating current i hrc - 431 - ? a v dd = 5 .5 v - 430 - ? a v dd = 3.3 v internal 10 khz low speed rc oscillator (lirc) 8.3.4.3 parameter sym. specifications test condition min. typ. max. unit supply voltage [1] v lrc 1.62 1.8 1.98 v center frequency f lrc - 10 - khz 25 ? c , v dd = 3 .3 v calibrated internal oscillator frequency - 30 - +30 % 25 ? c , v dd = 2.5 ~ 5.5 v - 50 - +50 % - 40 ? c ~+ 105 ? c , v dd = 2.5 ~ 5.5 v operating current i lrc - 0.74 - ? a v dd = 5.5 v 0.66 ? a v dd = 3 .3 v note: internal oscillator operation voltage comes from ldo.
nuc121 /125 feb . 23 , 201 7 page 135 of 150 rev 1 .0 0 nuc121 /125 series datasheet analog characteristics 8.4 8.4.1 12 - bit adc parameter sym. specifications test condition min. typ. max. unit operating voltage av dd 3.0 - 5.5 v av dd = v dd operating current (av dd current) (enable adc and disable all other analog modules) i adc 1 - 2.72 - m a av dd = v dd = 4.5 v a dc clock rate = 16 mhz i adc 2 ? a av dd = v dd = 2.5 v adc clock rate = 6 mhz resolution r adc - - 12 bit reference voltage v ref - av dd - v av dd = 5v adc input voltage v in 0 - av dd v adc clock frequency f adc - - 16 mhz av dd = 5 v - - 8 mhz av dd = 3 v acquisition time (sample stage) t acq 2 7 21 1/f adc default: 7 (1/fadc) conversion time t conv 15 20 34 1/f adc t conv = t acq + 13 default: 20 (1/fadc) conversion rate (f adc /t conv ) f sps - - 800 ksps a v dd = 5 v t conv = 20 clock f adc = 16 m h z - - 300 ksps av dd = 3 v t conv = 2 0 clock f adc = 6 m h z integral non - linearity error inl +1. 6 - +2. 1 lsb differential non - linearity dnl - 1 - - 1.5 lsb gain error e g - 3. 4 - - 4. 7 lsb offset error e offset +2. 2 - +3. 6 lsb absolute error e abs +3. 1 - +4. 7 lsb internal capacitance c in - 3.2 - pf input load r in - 6 - k monotonic - guaranteed -
nuc121 /125 feb . 23 , 201 7 page 136 of 150 rev 1 .0 0 nuc121 /125 series datasheet note: the inl is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal transfer curve. a calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve. typical connection diagram using the adc note: gnd < ain x < vdd 1 2 3 4 5 6 4 0 9 5 4 0 9 4 7 4 0 9 3 4 0 9 2 i d e a l t r a n s f e r c u r v e a c t u a l t r a n s f e r c u r v e o f f s e t e r r o r e o a n a l o g i n p u t v o l t a g e ( l s b ) 4 0 9 5 a d c o u t p u t c o d e o f f s e t e r r o r e o g a i n e r r o r e g e f ( f u l l s c a l e e r r o r ) = e o + e g d n l 1 l s b v d d 1 2 - b i t c o n v e r t e r a i n x r i n c i n ( 1 ) ( 1 )
nuc121 /125 feb . 23 , 201 7 page 137 of 150 rev 1 .0 0 nuc121 /125 series datasheet 8.4.2 ldo symbol parameter min typ max unit test condition v dd dc power supply 2.5 - 5.5 v v ldo output voltage 1.62 1.8 1.98 v t a temperature - 40 25 +105 note 1 : it is recommended a 0.1f bypass capacitor is connected between v dd and the closest v ss pin of the device. note 2 : for ensuring power stability, a 1f capacitor must be connected between ldo_cap pin and the closest v ss pin of the device. 8.4.3 low - voltage reset symbol parameter min typ max unit test condition av dd supply voltage 0 - 5.5 v t a temperature - 40 - +105 - i lvr quiescent current - 1.1 - ua av dd = 5.5v v por threshold voltage 2.1 2.2 2.3 v t a = 8 5 2.0 2.1 2.2 v t a = 25 1.9 2.0 2.1 v t a = - 40 t lvr_start start - up time - 129 - us 8.4.4 brown - out detector symbol parameter min typ max unit test condition a v dd supply voltage 0 - 5.5 v - t a temperature - 40 - +105 - i bod quiescent c urrent - 81 - a av dd = 5.5 v vbod brown - out voltage (falling edge) 4.3 4.5 4.7 v bodvl [1:0] = 11 3.5 3.7 3.9 v bodvl [1:0] = 1 0 2. 55 2.7 2. 85 v bodvl [1:0] = 0 1 2. 05 2.2 2. 35 v bodvl [1:0] = 00 vbod brown - out voltage 4.3 4.6 .4.7 v bodvl [1:0] = 11
nuc121 /125 feb . 23 , 201 7 page 138 of 150 rev 1 .0 0 nuc121 /125 series datasheet (rising edge) 3.6 3.8 4.0 v bodvl [1:0] = 1 0 2.6 2.75 2.9 v bodvl [1:0] = 0 1 2.1 2.25 2.4 v bodvl [1:0] = 00 t bod_start start - up time - 1060 - us 8.4.5 power - on reset symbol parameter min typ max unit test condition t a temperature - 40 - +105 - v por threshold voltage 1.5 2 2.2 v - v hys power drop detect v oltage 1.78 v figure 8.4 - 1 power - up ramp condition t ( d o n t c a r e ) v p o r v h y s
nuc121 /125 feb . 23 , 201 7 page 139 of 150 rev 1 .0 0 nuc121 /125 series datasheet 8.4.6 temperature sensor parameter sym. specifications test condition (supply voltage = 3v) min. typ. max. unit detection temperature t det - 40 - + 105 o c operating current i temp 6.4 - 10.5 ? a gain v tg - 1. 8 - 1. 7 6 - 1. 73 mv/ o c offset v to - 7 2 5 - mv temperature at 0 o c note 1 : internal operation voltage comes f rom ldo. note 2: the temperature sensor formula for the output voltage (vtemp) is as below equation. vtemp (mv) = gain (mv/ ) x temperature ( ) + offset (mv)
nuc121 /125 feb . 23 , 201 7 page 140 of 150 rev 1 .0 0 nuc121 /125 series datasheet 8.4.7 usb phy low - full - speed dc electrical specifications 8.4.7.1 symbol parameter min. typ. max. unit test conditions v ih input h igh (driven) 2.0 - - v - v il input l ow - - 0.8 v - v di differential i nput s ensitivity 0.2 - - v |padp - padm| v cm differential c ommon - mode r ange 0.8 - 2.5 v includes v di range v se single - ended r eceiver t hreshold 0.8 - 2.0 v - receiver h ysteresis - 200 - mv - v ol output l ow (driven) 0 - 0.3 v - v oh output h igh (driven) 2.8 - 3.6 v - v crs output s ignal c ross v oltage 1.3 - 2.0 v - r pu pull - up r esistor 1.425 - 1.575 k - r pd pull - down resistor 14.25 - 15.75 k v trm termination voltage for uptream port pull up (rpu) 3.0 - 3.6 v z drv driver o utput r esistance - 10 - steady state drive* c in transceiver c apacitance - - 20 pf pin to gnd *driver output resistance doesnt include series resistor resistance. usb full - speed driver electrical characteristics 8.4.7.2 symbol parameter min. typ. max. unit test conditions t fr rise time 4 - 20 ns c l =50p t ff fall time 4 - 20 ns c l =50p t frff rise and f all t ime m atching 90 - 111.11 % t frff =t fr /t ff usb ldo specification 8.4.7.3 symbol parameter min. typ. max. unit test conditions v bus v bus pin input voltage 4.0 5.0 5.5 v - v dd33 ldo output voltage 3.0 3.3 3.6 v - c bp external bypass capacitor - 1.0 - uf -
nuc121 /125 feb . 23 , 201 7 page 141 of 150 rev 1 .0 0 nuc121 /125 series datasheet flash dc electrical characteris 8.5 symbol parameter min typ max unit test condition v fla [1] supply voltage 1.62 1.8 1.98 v t a = 25 n endur endurance 20,000 - - cycles [2] t ret data retention 100 - - year t erase page erase time 20 - 40 ms t m e r mass erase time 20 - 40 ms t prog program time 20 - 40 us i dd1 read current - - tbd ma i dd2 program current - - tbd ma i dd3 erase current - - tbd u a note 1: v fla is source from chip ldo output voltage. note 2: number of program/erase cycles. note 3 : this table is guaranteed by design, not test in production.
nuc121 /125 feb . 23 , 201 7 page 142 of 150 rev 1 .0 0 nuc121 /125 series datasheet i 2 c dynamic characteristics 8.6 symbol parameter standard m ode [1][2] fast m ode [1][2] unit min . max . min . max . t low scl low period 4.7 - 1.2 - us t high scl high period 4 - 0.6 - us t su; sta repeated start condition setup time 4.7 - 1.2 - us t hd; sta start condition hold time 4 - 0.6 - us t su; sto stop condition setup time 4 - 0.6 - us t buf bus free time 4.7 [3] - 1.2 [3] - us t su;dat data setup time 250 - 100 - ns t hd;dat data hold time 0 [4] 3.45 [5] 0 [4] 0.8 [5] us t r scl/sda rise time - 1000 20+0.1c b 300 ns t f scl/sda fall time - 300 - 300 ns c b capacitive load for each bus line - 400 - 400 pf notes : 1. guaranteed by design, not tested in production. 2. hclk must be higher than 2 mhz to achieve the maximum standard mode i 2 c frequency. it must be higher than 8 mhz to achieve the maximum fast mode i 2 c frequency. 3. i 2 c controller must be retriggered immediately at slave mode after receiving stop condition. 4. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the u ndefined region of the falling edge of scl. 5. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. figure 8.6 - 1 i 2 c timing diagram t b u f s t o p s d a s c l s t a r t t h d ; s t a t l o w t h d ; d a t t h i g h t f t s u ; d a t r e p e a t e d s t a r t t s u ; s t a t s u ; s t o s t o p t r
nuc121 /125 feb . 23 , 201 7 page 143 of 150 rev 1 .0 0 nuc121 /125 series datasheet spi dynamic characteristics 8.7 8.7.1 dynamic characteristics of data input and output pin symbol parameter min . typ . max . unit spi m aster m ode (vdd = 4.5 v ~5.5 v, 30 pf loading capacitor ) t ds data setup time 4 2 - ns t dh data hold time 0 - - ns t v data output valid time - 7 11 ns spi m aster m ode (vdd = 3 . 0~3.6 v, 30 pf loading capacitor ) t ds data setup time 5 3 - ns t dh data hold time 0 - - ns t v data output valid time - 13 18 ns figure 8.7 - 1 spi master mode timing diagram symbol parameter min . typ . max . unit spi s lave m ode (vdd = 4.5 v ~5.5 v, 30 pf loading capacitor ) t ds data setup time 0 - - ns t dh data hold time 2*pclk+4 - - ns t v data output valid time - 2*pclk+11 2*pclk+19 ns spi s lave m ode (vdd = 3 . 0 v ~ 3 . 6 v, 30 pf loading capacitor ) c l k p = 0 , t x _ n e g = 1 , r x _ n e g = 0 o r c l k p = 1 , t x _ n e g = 0 , r x _ n e g = 1 c l k p = 0 , t x _ n e g = 0 , r x _ n e g = 1 o r c l k p = 1 , t x _ n e g = 1 , r x _ n e g = 0 m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d s p i c l k m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d c l k p = 0 c l k p = 1 t v t d s t d h t v t d s t d h
nuc121 /125 feb . 23 , 201 7 page 144 of 150 rev 1 .0 0 nuc121 /125 series datasheet t ds data setup time 0 - - ns t dh data hold time 2*pclk+6 - - ns t v data output valid time - 2*pclk+19 2*pclk+25 ns figure 8.7 - 2 spi slave mode timing diagram c l k p = 0 , t x _ n e g = 1 , r x _ n e g = 0 o r c l k p = 1 , t x _ n e g = 0 , r x _ n e g = 1 c l k p = 0 , t x _ n e g = 0 , r x _ n e g = 1 o r c l k p = 1 , t x _ n e g = 1 , r x _ n e g = 0 m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d s p i c l k m i s o m o s i d a t a v a l i d d a t a v a l i d d a t a v a l i d d a t a v a l i d c l k p = 0 c l k p = 1 t v t d s t d h t v t d s t d h
nuc121 /125 feb . 23 , 201 7 page 145 of 150 rev 1 .0 0 nuc121 /125 series datasheet 9 package dimensions lqfp 64 s (7x7x1.4 mm) 9.1
nuc121 /125 feb . 23 , 201 7 page 146 of 150 rev 1 .0 0 nuc121 /125 series datasheet lqfp 48l (7x7x1.4 mm) 9.2 1 12 48 h h ? controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 9.10 9.00 8.90 0.358 0.354 0.350 0.50 0.20 0.25 1.45 1.40 0.10 0.15 1.35 0.008 0.010 0.057 0.055 0.026 7.10 7.00 6.90 0.280 0.276 0.272 0.004 0.006 0.053 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 7 0.020 0.35 0.65 0.10 0.05 0.002 0.004 0.006 0.15 9.10 9.00 8.90 0.358 0.354 0.350 7.10 7.00 6.90 0.280 0.276 0.272 0.014 37 36 25 24 13
nuc121 /125 feb . 23 , 201 7 page 147 of 150 rev 1 .0 0 nuc121 /125 series datasheet qfn 33 z (5x5x0.8 mm) 9.3
nuc121 /125 feb . 23 , 201 7 page 148 of 150 rev 1 .0 0 nuc121 /125 series datasheet
nuc121 /125 feb . 23 , 201 7 page 149 of 150 rev 1 .0 0 nuc121 /125 series datasheet 10 revision history revision date description 1 . 00 201 7 . 0 2 . 1 5 preliminary v ersion
nuc121 /125 feb . 23 , 201 7 page 150 of 150 rev 1 .0 0 nuc121 /125 series datasheet important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, insecure usage. insecure usag e includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instrume nts, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, custome r shall indemnify the damages and liabilities thus incurred by nuvoton.

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